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Techwell, Inc. TW9903 - Multi-standard Video Decoder With High Quality Down Scaler Preliminary Data Sheet
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TW9903
Introduction and Features....................................................3 Functional Description.........................................................4 Overview ...........................................................................5 Analog Front-end...............................................................5 Video Source Selection...................................................5 Clamping and Automatic Gain Control.............................6 Analog to Digital Converter..............................................6 Sync Processing................................................................6 Horizontal sync processing .............................................6 Vertical sync processing.................................................7 Color Decoding..................................................................7 Y/C separation...............................................................7 Color demodulation ........................................................7 Automatic Chroma Gain Control......................................8 Low Color Detection and Removal..................................8 Automatic standard detection..........................................8 Video Format support .....................................................9 Component Processing......................................................9 Luminance Processing...................................................9 Gamma .........................................................................9 Sharpness.....................................................................9 The Hue and Saturation................................................10 Closed Caption Decoding.................................................10 Power Management.........................................................10 Control Interface..............................................................10 Output Interface...............................................................11 Clock and Control Signal Output....................................12 HSYNC, VSYNC and FIELD.........................................13 HACTIVE.....................................................................15 VACTIVE.....................................................................16 LVALID........................................................................16 DVALID and VCLK.......................................................17 CbCr data and CBFLAG...............................................19 CLKX2 and CLKX1.......................................................20 ITU-R BT.656...............................................................20 Down-scaling and Cropping ..........................................21 TW9903 Down -Scaling.................................................21 TW9903 Cropping........................................................22 VBI Data Processing........................................................24 TW9903 VBI Overview .................................................24 VBI Frame Output Mode...............................................25 VBI Byte Order.............................................................25 Closed Captioning and Extended Data Services ................25 Two Wire Serial Bus Interface...........................................27 Test Modes .....................................................................30 Filter Curves ....................................................................31 Decimation filter............................................................31 Chroma Band Pass Filter Curves ..................................31 Luma Notch Filter Curve for NTSC and PAL/SECAM.....32 Chrominance Low -Pass Filter Curve.............................32 Horizontal Scaler Pre- Filter curves ................................33 Vertical Interpolation Filter curves..................................33 Peaking Filter Curves....................................................34 Control Register.................................................................35 TW9903 Register SUMMARY .......................................35 0x00 - Product ID Code Register (ID)...........................36 0x01 - Chip Status Register (CSTATUS).......................37 0x02 - Input Format (INFORM) .....................................38 0x03 - Output Format Control Register (OPFORM) .......39 0x04 - GAMMA and HSYNC Delay Control...................39 0x05 - Output Polarity Register (POLARITY).................40 0x06 - Analog Control Register (ACNTL).......................41 0x07 - Cropping Register, High (CROP_HI) ..................41 0x08 - Vertical Delay Register, Low (VDELAY_LO) .......42 0x09 - Vertical Active Register, Low (VACTIVE_LO)......42 0x0A - Horizontal Delay Register, Low (HDELAY_LO)...42 0x0B - Horizontal Active Register, Low (HAC TIVE_LO) .42 0x0C - Control Register I (CNTRL1)..............................43 0x0D - Vertical Scaling Register, Low (VSCALE_LO)....43 0x0E - Scaling Register, High (SCALE_HI) ...................44 0x0F - Horizontal Scaling Register, Low (HSCALE_LO) 44 0x10 - BRIGHTNESS Control Register (BRIGHT) .........44 0x11 - CONTRAST Control Register (CONTRAST) ......44 0x12 - SHARPNESS Control Register I (SHARPNESS) 45 0x13 - Chroma (U) Gain Register (SAT_U)...................45 0x14 - Chroma (V) Gain Register (SAT_V) ...................45 0x15 - Hue Control Register (HUE) ...............................46 0x16 - Sharpness Control Register II ............................ 46 0x17 - Reserved..........................................................46 0x18 - Coring Control Register (CORING) ....................46 0x19 - VBI Control Register (VBICNTL)........................47 0x1A - CC/EDS Status Register (CC_STATUS)............48 0x1B - CC/EDS Data Register (CC_DATA).................. 48 0x1C - Standard Selection (SDT) .................................49 0x1D - Standard Recognition (SDTR)...........................50 0x1E - General Programmable I/O Register (GPIO) ......50 0x1F - Test Control Register (TEST).............................51 0x20 - Clamping Gain (CLMPG)...................................51 0x21 - Individual AGC Gain (IAGC) ..............................52 0x22 - AGC Gain (AGCGAIN)......................................52 0x23 - White Peak Threshold (PEAKWT) .....................52 0x24- Clamp level (CLMPL).........................................52 0x25- Syn Amplitude (SYNCT)...................................52 c 0x26 - Sync Miss Count Register (MISSCNT) ...............53 0x27 - Clamp Position Register (PCLAMP) ...................53 0x28 - Vertical Control Register....................................53 0x29 - Vertical Control II...............................................54 0x2A - Color Killer Level Control...................................54 0x2B - Comb Filter Control...........................................54 0x2C - Luma Delay and HSYNC Control ......................54 0x2D - Miscellaneous Control Register I (MISC1)..........55 0x2E - Miscellaneous Control Register II (MISC2).........55 0x2F - Miscellaneous Control III (MISC3)......................56 0x30 - Macrovision Detection....................................... 57 0x31 - Clamp Cntl2......................................................57 0x32 - FILL DATA.......................................................58 0x33 - VBI CNTL1.......................................................58 0x34 - VBI CNTL2.......................................................58 0x35 - MISC 4.............................................................58 0x36 - Slice Level........................................................59 0x37 - WSS1...............................................................59 0x38 - WSS2...............................................................59 0x39 - CSTATUS III....................................................59 0x3A - HFREF ............................................................ 60 0x3B - CLAMP MODE.................................................60 Pin Diagram........................................................................61 Pin Description................................................................62 Analog Interface Pins ...................................................62 Two Wire Interface Pins................................................63 Video Timing Unit Pins .................................................63 Clock Interface Pins .....................................................65 Test Pins .....................................................................65 Power and Ground Pins ...............................................66 Parametric Information......................................................67 AC/DC Electrical Parameters ...........................................67 Clock Timing Diagram.................................................. 69 Application Information.....................................................70 Video Input Interface....................................................70 A/D Converter..............................................................70 Clamping/AGC.............................................................70 Clock Generation.........................................................70 Power-Up....................................................................70 Application Schematics....................................................71 PCB Layout Considerations ..........................................72 100-pin PQFP Package Mechanical Drawing ....................73 100-pin LQFP Package Mechanical Drawing....................74
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TW9903
TW9903 - NTSC/PAL/SECAM Analog to Digital Video Decoder with High Quality Scaler
Introduction and Features
Techwell's TW9903 is a high quality NTSC, PAL, and SECAM video decoder plus high quality down scaler designed for multimedia applications. TW9903 uses the mixed-signal 3.3V CMOS technology to provide a low-cost and low-power integrated solution. Minimum external components are required due to its integrated analog front -end containing AGC, clamping, and three 8-bit high speed ADCs. For composite inputs, an adaptive comb filter and luma/chroma processing produce exceptionally high quality pictures using proprietary techniques. A high quality internal scaling engine offers arbitrarily filtered down scaling of the output picture. A built-in Closed-Caption decoder and VBI data pass-through support data applications such Closed-Captioning and IntercastTM.
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- - - - - - - - -
Video processing
Switchable Notch or 2H comb filter Y/C separation PAL delay line for color phase error correction Image enhancement with programmable peaking. Digital sub-carrier PLL for accurate color decoding Digital Horizontal PLL and advanced synchronization processing for non-standard video signals Programmable hue, brightness, saturation, and contrast. Automatic color control and color killer High quality horizontal and vertical filtered scaling with arbitrary scale down ratio Detection of level of copy protection according to Macrovision standard
Analog Video Decoder
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NTSC (M, 4.34) and PAL (B, D, G, H, I, M, N, N combination), PAL (60), SECAM with automatic format detection Advanced synchronization processing for VCR fast forward, backward, and pause mode Software selectable analog inputs allows any of the following combinations:
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Video Output
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Programmable output cropping VMI 1.4 compatible 8 -bit or 16-bit pixel interface ITU-R 601 or ITU-R 656 compatible output YCbCr(4:2:2) output format Clos ed caption decoding VBI data pass through, raw ADC data for IntercastTM
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Up to four composite video inputs Three composite and one S-video inputs
Miscellaneous
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- Two 8 -bit ADCs and analog clamping circuit. - Fully programmable static gain or automatic gain control for the Y or CVBS channel - Programmable white peak control for the Y or CVBS channel
Two wire MPU serial bus interface Power-down mode Typical power consumption 0.4W Single 27MHz crystal for all standards Supports 24.54MHz and 29.5MHz crystal for high resolution square pixel format 5V tolerant I/O 3.3 V power supply 100-pin PQFP package
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Functional Description
Figure 1: TW9903 Block Diagram
Chroma Demodulation
V
Analog Video In
Clamp
MUX
8-bit ADC
Filter
C(0) C(1)
U
Luma/Chroma processor
H/V Down Scaler/Cropping
AGC/Clamp
Filter
MUXin0 MUXin1 (1) MUXin2 MUXin3 TRST TCK TMS TDI TDO
2-H adaptive comb filter or Notch/ bandpass Y/C separation
8-bit ADC
Yin MUXOUT
Y
VD(15:8) VD(7:0) MPOUT CBFLAG VCLK
MUX
Sync Processor
Video Interface
VSYNC HSYNC FIELD VACTIVE HACTIVE DVALI D CLKx2 CLKx1
Test
27 Mhz
Clock
Closed Caption Decoder
VBI Pass through
PDN OE
2 Wire Serial Bus
SIAD1 SIAD0 SDA SCLK
CCVALID
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TW9903 Overview
Techwell's TW9903 is a high quality NTSC/PAL/SECAM video decoder that is designed for multimedia applications. It uses the mixed-signal 3.3V CMOS technology to provide a low-power integrated solution. The TW9903 analog front-end is equipped with three separate analog channels that enable it to accept two possible analog video signal standards: composite or S-video. All channels include an analog multiplexer (MUX) for maximum flexibility in software controlled input selection. It is possible to connect up to four composite inputs at one time and allow the software to switch between them. Alternatively several combinations of c omposite inputs and S-Video component inputs may be switched under software control. (Four input channels of any format can be accommodated with but there is a maximum of 2 S-Video inputs and 2 component inputs.) The front-end contains all the necessary circuits to simplify the system design. AGC and clamping circuits, and three 8 analog-to-digital converters (ADCs) convert inputs into digital signals for -bit processing. The TW9903 uses proprietary adaptive comb filter for chroma and luma separation to achi eve high video quality. The image enhancement uses nonlinear methods to enhance picture sharpness with little overshoot. The advanced synchronization processing can produce stable pictures for non-standard signal such as those produced by VCR during fast forward, rewind or pause. The high quality scaler uses multi-tap poly-phase decimation filter to reduce aliasing effects. It can be programmed to scale-down the output picture to an arbitrary ratio with cropping. The TW9903 supports flexible pixel int erface. It outputs YCbCr (4:2:2) data stream over 8 or -bit 16-bit data path. The output is VMI 1.4 compatible. A 2-wire serial MPU interface is used to simplify system integration. All the functions can be controlled through this interface.
Analog Front-end
The analog front-end converts analog video signals to the required digital format. There are three analog channels with clamping circuits and ADCs. The Y channel has 4-input multiplexer, and a variable gain amplifier for automatic gain control (AGC). ts four inputs are identified as MUX0, I MUX1, MUX2 and MUX3. The C_Pb channel has 2-input multiplexer. Its two inputs are identified as C_PbIn0 and C_PbIn1. The C_Pb channel is internally clamped to the zero level of the bipolar input source when enabled. Video Source Selection All analog signals should be AC-coupled to these inputs. The Y channel analog multiplexer selects one of the four inputs MUX[0-3]. MUX[0-3] can be connected to composite video inputs or the Y signal of an S-Video or component input. When decoding a S-Video input, the Y signal should connect to one of the MUX inputs and the C signal to C_PbIn0 or C_PbIn1.
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Software selectable analog inputs allow several possible input combinations: 1. Up to four composite video inputs. 2. Three composite, one S-video. The input video signals in any certain channel maybe momentarily connected together through the equivalent of a 200 ohm resistor during multiplexer switching. Therefore, the multiplexer cannot be used for switching on a real-time pixel-by-pixel basis. Clamping and Automatic Gain Control All three analog channels have built-in clamping circuit that restore the signal DC level. The Y channel restores the back porch of the digitized video to a level of 64 or a programmable level. The C_Pb channel restores the back porch of the digitized video to a level of 128. This operation is automatic through internal feedback loop. The Automatic Gain Control (AGC) of the Y channel adjusts input gain so that the sync tip is at a desired level. A programmable white peak protection logic is included to prevent saturation in the case of abnormal proportion between sync and white peak level. Analog to Digital Converter TW9903 contains three 8 pipelined ADCs that consume less power than conventional flash -bit ADC. The output of the Clamp and AGC connects to one ADC that digitizes the composite input or the Y signal of the S-Video input. The second ADC digitizes the C signal when decoding S-video signal.
Sync Processing
The sync processor of TW9903 detects horizontal synchronization and vertical synchronization signals in the composite video or in the Y signal of an S-video or component signal. The processor contains a digital phase-locked-loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals such as those from VCR fast forward or backward. Horizontal sync processing The horizontal synchronization processing contains a sync separator, a phase-locked-loop (PLL), and the related decision logic. The horizontal sync detector detects the presence of a horizontal sync tip by examining low-pass filtered input samples whose level is lower than a threshold. After sufficient low levels are detected, a horizontal sync is recognized. Additional logic is also used to avoid false detection on glitches. The horizontal PLL locks onto the extracted horizontal sync in all conditions to provide jitter free image output. From there, the PLL also provides orthogonal sampling raster for the down stream processor. The PLL has free running frequency that matches the standard raster frequency. It also has wide lock-in range for tracking any non-standard video signal.
In case the horizontal sync is missing, a "free-wheel" mechanism keeps generating horizontal sync signal until horizontal sync is detected again. This option can also be turned off for some applications that determine video loss by detecting the existence of horizontal sync.
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Vertical sync processing The vertical sync separator detects the vertical synchronization pattern in the input video signals. In addition, the actual sync determination is controlled by a detection window to provide more reliable synchronization. It achieves the functionality of a PLL without the complexity of a PLL. An option is available to provide faster responses for certain applications. The field status is determined at vertical synchronization time. When the location of the detected vertical sync is inline with a horizontal sync, it indicates a frame start or the odd field start. Otherwise, it indicates an even field. The field logic can also be controlled to toggle automatically while tracking the input.
Color Decoding
Y/C separation The color-decoding block contains the luma/chroma separation for the composite video signal and multi-standard color demodulation. For NTSC and PAL standard signals, the luma/chroma separation can be done either by comb filter or notch/band-pass filter combination. For SECAM standard signals, only notch/band-pass filter is available. The default selection for NTSC/PAL is comb filter. The characteristics of the band-pass filter is shown in the filter curve section. In the case of comb filter, the TW9903 separates luma (Y) and chroma (C) of a NTSC composite video signal using a proprietary 2H adaptive comb filter. The filter uses a two-line buffer. Adaptive logic combines the upper-comb and the lower-comb results based on the signal changes among the previous, current and next lines. This technique leads to good Y/C separation with small cross luma and cross color at both horizontal and vertical edges. Due to the 90-degree phase difference on adjacent lines of a PAL chroma signal, the 2H line memory are used optionally to provide an adequate PAL comb filter performance. Due to the line buffer used in the comb filter, there is always one line processing delay in the output images in general except the PAL comb filter case, which has no line delay. If notch/band-pass filter is selected, the characteristics of the filters are shown in the filter curve section. Color demodulation The color demodulation for NTSC and PAL standard is done by first quadrature mixing the chroma signal to the base band. The mixing frequency is equal to the sub-carrier frequency for NTSC and PAL. After the mixing, a low-pass filter is used to remove carrier signal and yield chroma components. The low-pass filter characteristic can be selected for optimized transient color performance. For the PAL system, the PAL ID or the burst phase switching is identified to aid the PAL color demodulation. For SECAM, the mixing frequency is 4.286Mhz. After the mixer and low-pass filter, it yields the FM modulated chroma. The SECAM demodulation process therefore consists of low-pass filter, FM demodulator and de-emphasis filter. The filter characteristics are shown in filter curve section. During the FM demodulation, the chroma carrier frequency is identified and used to control the SECAM color demodulation. The sub-carrier signal for use in the color demodulator is generated by direct digital synthesis PLL that locks onto the input sub-carrier reference (color burst). This arrangement allows any substandard of NTSC and PAL to be demodulated easily with single crystal frequency.
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During S-video operation, the Y signal bypasses the comb filter. The C_Pb signal connects directly to the color demodulator. During component input operation, all the chroma processing and color demodulator blocks are bypassed. Automatic Chroma Gain Control The Automatic Chroma Gain Control (ACC) compensates for reduced amplitudes caused by highfrequency loss in video signal. In the NTSC/PAL standard, the color reference signal is the burst on the back porch. This color-burst amplitude is calculated and compared to standard amplitude. The chroma (Cx) signals are then increased or decreased in amplitude accordingly. The range of ACC control is -6db to +24db. This function is always enabled to provide consistent image quality under different signal conditions. Low Color Detection and Removal For low color amplitude signals, black and white video, or very noisy signals, the color will be "killed". The color killer uses the burst amplitude measurement to switch-off the color when the measured burst amplitude falls below a programmed threshold. The threshold has programmed hysteresis to prevent oscillation of the color killer function. The color killer function can be disabled by programming a low threshold value. Automatic standard detection The TW9903 has build-in automatic standard discrimination circuitry. The circuit uses burst -phase, burst-frequency and frame rate to identify NTSC, PAL or SECAM color signals. The standards that can be identified are NTSC (M), NTSC (4.43), PAL (B, D, G, H, I), PAL (M), PAL (N), PAL (60) and SECAM (M). Each standard can be included or excluded in the standard recognition process by software control. The identified standard is indicated by the Standard Selection (SDT) register. Automatic standard detection can be overridden by software controlled standard selection.
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Video Format support TW9903 supports all common v ideo formats as shown in Table 1. The video decoder needs to be programmed appropriately for each of the composite video input formats. Table 1. Video Input Formats Supported by the TW9903
Format NTSC-M NTSC-Japan (1) PAL-B, G, N PAL-D PAL-H PAL-I PAL-M PAL-CN SECAM PAL-60 NTSC (4.43) Lines 525 525 625 625 625 625 625 625 625 525 525 Fields 60 60 50 50 50 50 60 50 50 60 60 Fsc 3.579545 MHz 3.579545 MHz 4.433619 MHz 4.433619 MHz 4.433619 MHz 4.433619 MHz 3.575612 MHz 3.582056 MHz 4.406MHz 4.250MHz 4.433619 MHz 4.433619 MHz Country U.S., many others Japan Many China Belgium Great Britain, others Brazil Argentina France, Eastern Europe, Middle East, Russia China Transcoding
Notes: (1). NTSC-Japan has 0 IRE setup.
Component Processing
Luminance Processing The TW9903 adjusts brightness by adding a programmable value (in register BRIGHTNESS) to the Y signal. It adjusts the picture contrast by changing the gain (in register CONTRAST) of the Y signal. The TW9903 video decoder also performs a coring function. It can force all values below a certain level, programmed in the Coring Control Register, to zero. This is useful because human eyes are sensitive to variations in nearly black images. Changing levels near black to true black, can make the image appears clearer. Gamma Y Gamma function is provided to compensate for different display types. Four pre-programmed Gamma levels can be selected through registers. Sharpness The TW9903 also provides a sharpness control function through control registers. It p rovides the control in 16 steps up to +12db. The center frequency of the enhancement curve is around 3.5Mhz. It also provides a high frequency coring function to minimize the amplification of high frequency noise. The coring level is adjustable through the Coring Control register. The same function can also be used to soften the images. This can be used to provide noise reduction on noisy signal.
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To further enhance the image, a programmable vertical peaking function is provided for up to +6db of enhancement. A programmable coring level can be adjusted to minimize the noise enhancement. The Hue and Saturation When decoding NTSC signals, TW9903 can adjust the hue of the chroma signal. The hue is defined as a phase shift of the subcarrier with respect to the burst. This phase shift can be programmed through a control register. The color saturation can be adjusted by changing the gain of Cb and Cr signals for all NTSC, PAL and SECAM formats. The Cb and Cr gain can be adjusted independently for flexibility.
Closed Caption Decoding
TW9903 has a built-in Closed Caption (CC) and Extended Data Services (EDS) decoder that adheres to the EIA-608 standard. This decoder can be enabled or disabled independently on line 21 and line 284 for NTSC. The decoded data is made available through CC_DATA and CC_STATUS registers that can be accessed through the 2-WIRE SERIAL MPU interface.
Power Management
The TW9903 can be put into power-down mode in which its clock is turned off for most of the circuits. The Y, C/Pr and Pb path can be separately powered down.
Control Interface
The TW9903 registers are accessed via 2 -WIRE SERIAL MPU interface. It operates as a slave device. Serial clock and data lines, SCL and SDA, transfer data from the bus master at a rate of 400 Kbits/s. The TW9903 has two serial interface address select pins to program up to four unique serial addresses TW9903. This allows as many as four TW9903 to share the same serial bus. Reset signals are also available to reset the control registers to their default values.
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Output Interface
HSYNC VSYNC HACTIVE VACTIVE DVALID MPOUT VCLK FIELD CBFLAG CLKX1, CLKX2 OE# VD[15:0]
TW9903
Figure 2. TW9903 Video Data Output Interface The TW9903 supports a synchronous 8-bit or 16-bit YCbCr 4:2:2 data output stream. The interface consists of VD [15:0], HSYNC, VSYNC, HACTIVE, VACTIVE, DVALID, MPOUT, VCLK, FIELD, CBFLAG, and OE# as shown in Figure 2. In 8-bit output mode, Reg0x03[6] is "0".In 16-bit output mode,Reg0x03[6] is "1". The TW9903 outputs all pixel data and control signals synchronous with CLKX2 rising edge for both the 8-bit format and the 16bit format. The mapping of video data stream formats is shown in Table 2. When the output is configured for a 8-bit format, the data is output on pins VD[15:8] with 8 bits of chrominance data preceding 8 bits of luminance data for each pixel output. The data output is synchronous to the rising edge of CLKX2. When the output s configured for a 16 -bit format, the luminance data is output on VD[15:8], and i the chrominance data is output on VD[7:0]. In 16-bit mode, the data output is synchronous with the rising edge of CLKX2 and VD[15:0] data changes when CLKX1 goes high. Figure3a shows 8-bit video data output timing. Figure3b shows 16-bit video data output timing.
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Pin Name VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
CK1 2N Y7 Y6 Y6 Y5 Y5 Y4 Y4 Y3 Y3 Y2 Y2 Y1 Y1 Y0 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0
2N+1 Y7 CK2 4N
Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 Y6 Cr6 Y6 Y5 Cr5 Y5 Y4 Cr4 Y4 Y3 Cr3 Y3 Y2 Cr2 Y2 Y1 Cr1 Y1 Y0 Cr0 Y0
4N+1 Y7 4N+2 Cr7 4N+3 Y7
ITU-R BT.656
SAV and EAV sequence, YCbCr data and blanking data are transferred on these pins
Table 2. Output mapping between various data formats
CLKX2 CLKX1 VD[15:8] Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 Cb6 Y6 Cr6
Figure 3a. 8-bit Video Data Output timing
CLKX2 CLKX1 VD[15:8] Y0 Y1 Y2 Y3 Y4 Y5 Y6
VD[7:0]
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Cb6
Figure 3b. 16-bit Video Data Output Timing Clock and Control Signal Output The default output format of TW9903 is a synchronous 8-bit YCbCr 4:2:2 data format with separate syncs and flags. Video data is compliant with ITU-601format. HSYNC, VSYNC, HACTIVE, VACTIVE, LVALID (MPOUT), FIELD have the same output timings in both 8-bit output mode and 16-bit output modes. All control signals are synchronous with the rising edge of CLKX2.and they are illustrated with default polarity register setting values bellow.
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HSYNC, VSYNC and FIELD The HSYNC and VSYNC output timing is VMI v1.4 compliant. The leading edge of HSYNC depends on the input video signal. The pulse width of HSYNC is programmable from 8-128 CLKX1 cycles. The leading edge of VSYNC also depends on the video input. It typically occurs on the low period of first serration pulse of the video signal. The trailing edge of VSYNC follows the HSYNC in order to be VMI compliant. For the start of the odd field, it occurs 64 CLKX2 cycles after the trailing edge of HSYNC that follows the last equalization pulse of the input. For the indication of the even field, the trailing edge of VSYNC occurs 64 CLKX2 cycles after the leading edge of HSYNC that follows the last equalization pulse of the input. In this latter case, the HSYNC width has to be set at least 64 CLKX1 cycles. The FIELD output indicates the input v ideo source field state as determined by the decoder. It changes state at the leading edge of VSYNC to reflect the state of following field. If the field cannot be determined due to video source noise, it will toggle its state for each field until it can be corrected by the source. Figure4 shows HSYNC output timing. HSYNC changes when CLKX1 goes high. Figure 5a shows Odd field VSYNC and HSYNC Timing. Figure 5b shows Even field VSYNC and HSYNC timing. Figure 6 shows FIELD and VSYNC Timing. The leading edge of VSYNC changes with FIELD signal. The video timing of these outputs is also illustrated in Figure 7a and 4b.
CLKX2 CLKX1 HSYNC
Changed by HSLEN
Figure 4 HSYNC output timing
FIELD(0) HSYNC VSYNC 64 CLKX2 Clocks
Fgure 5a. Odd field VSYNC and HSYNC timing
FIELD(1) HSYNC VSYNC 64 CLKX2 Clocks
Figure 5b. Even field VSYNC and HSYNC timing
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VSYNC FIELD
Figure 6. VSYNC and FIELD timing
1
INPUT HSYNC VSYNC FIELD ODD
264
INPUT HSYNC VSYNC FIELD EVEN
Figure 7a. HSYNC, VSYNC and FIELD timing for NTSC field transition
1
INPUT HSYNC VSYNC FIELD ODD
314
INPUT HSYNC VSYNC FIELD EVEN
Figure 7b. HSYNC, VSYNC and FIELD timing for PAL(B,D,G,H,I) field transition
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TW9903
HACTIVE TW9903 outputs two type of HACTIVE signal on HACTIVE pin. TW9903 maintains video HACTIVE and VBI HACTIVE internally. If VBI EN(Reg0x19[7]) is set to "1 TW9903 outputs VBI ", HACTIVE on VBI output line. TW9903 outputs VBI HACTIVE on the line that LVALID is high and VACTIVE is low. If RTSEL(Reg0x19[2:0]) is set to 0x7,LVALID signal can be observed on MPOUT pin. TW9903 outputs video HACTIVE except VBI line on HACTIVE pin. TW9903 outputs video HACTIVE in whole line per frame or some lines selected by HA_EN(Reg0x19[4]) and VSCTL(Reg0x03[3]). During the lines that VACTIVE is low, if HA_EN is set to "1", TW9903 outputs video HACTIVE, if HA_EN is set to "0', TW9903 doesn output video HACTIVE. During those lines 't that VACTIVE is high and LVALID is low, if VSCTL is set to "1", TW9903 outputs video HACTIVE. If VSCTL is set to "0", TW9903 doesn't output video HACTIVE. In VBI enable mode (Reg0x19[7]=1), VBI HACTIVE has higher priority than video HACTIVE in VBI output line. The video HACTIVE is asserted at the start of the active video synchronous to the rising edge of CLKX2. . When the horizontal count of CLKX1 cycles matches the setting of HDELAY register, video HACTIVE is asserted. It will be asserted for a period matches the setting of HACTIVE register before it is de-asserted. HACTIVE signal changes when CLKX1 goes to high. If BYPASS Register bit is set to "0 the number of CLKX2 clocks from the leading edge of HSYNC to the ", leading edge of video HACTIVE is always fixed during active video lines. Figure 8 shows video HACTIVE timing. Figure 9a shows VBI HACTIVE timing at the first VBI line. Figure 9b shows VBI HACTIVE timing during VBI output line. Figure 9c shows VBI HACTIVE timing at the last VBI line.
CLKX2 CLKX1 HACTIVE
Figure 8. VIDEO HACTIVE timing
HSYNC HACTIVE
8 CLKX2 Clocks LVALID VACTIVE(0)
Figure 9a . VBI HACTIVE timing at the first VBI line
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TW9903
HSYNC
HACTIVE
8 CLKX2 Clocks LVALID(1)
VACTIVE(0)
Figure 9b. VBI HACTIVE timing during VBI lines
VBI LINE HSYNC HACTIVE LVALID VACTIVE
ACTIVE VIDEO LINE
X
X changes by Vertical Down Scaling Setting.
Figure 9c. VBI HACTIVE timing at the last VBI line VACTIVE VACTIVE is used to indicate the start of active video line. When the line count in each field matches the VDELAY register setting, VACTIVE is asserted. It will remain asserted for the number of scan lines that match the setting of VACTIVE register before it is de-asserted. VACTIVE changes at the leading edge of HSYNC as illustrated in Figure 9c. Figure 10 also shows VACTIVE timing. LVALID LVALID is used to indicate the valid line of video line. If VBI EN(Reg0x19[7]) is set to "1', LVALID goes high from VBI start line(line 10 in 525 line video system and line 6 in 625 line video system) to the start line of active video line. If VBI EN(Reg0x19[7]) is set to "0", LVALID keeps low during the same lines. When VACTIVE is asserted and active video line is a valid line as determined by Vertical down scaling, LVALID stays high for the line. If active video line is not a valid line as determined by Vertical down scaling, LVALID stays low for the line. LVALID changes at the leading edge of HSYNC as shown in Figure 9a and 9c. Figure 10 also shows LVALID timing of typical vertical down scaling output mode.
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TW9903
HSYNC
Start Line
VACTIVE LVALID
VBI LINE
Changed by VDELAY Start Line in both odd and even field :
Changed by VACTIVE
6(625 line video system) 10(525 line video system)
LVALID in VBI LINE is always high if VBI EN is "1".
Figure 10. VACTIVE and LVALID timing DVALID and VCLK In a 601 pixel format, the active video resolutions are either 720 x 480 for the 525/60 video systems or 720 x 576 for the 625/50 systems. In a square pixel operation, the active video resolutions are either 640 x 480 for the 525/60 video systems or 768 x 576 for the 625/50 systems. The DVALID is used to indicate the valid active pixels data output during a active video line. DVALID is also used to indicate valid VBI data. If VBI EN(Reg0x19[7]) is set to "1',DVALID always has valid timing while HACTIVE is active . The DVALID can be configured to output in three different formats. This is determined by the DVALID (0x03[5:4] ) register. In the first format, the DVALID output is asserted for valid pixel during the valid pixel time on video lines. The VCLK is gated by DVALID for proper pixel data strobing. For 8-bit output mode, VCLK is the inverted CLK2 and masked to "0" value while DVALID is invalid in order to indicate valid pixel data. For 16-bit output mode, CLKX1 is used instead of CLK2. In the second format, the DVALID output has the same timing as the first format s. VCLK is ' inverted CLKX2 or CLKX1. In 8 output mode, LEN(Reg0x3[6]=0),VCLK is inverted CLKX2.In -bit 16-bit output mode, LEN(Reg0x03[6]=1),VCLK is inverted CLKX1. In the third format, the DVALID has the same timing as VCLK of the first format. VCLK has the same timing as the second format's. VCLK wave changes by LEN(Reg0x03[6]) setting. If LEN is set to "1 its wave form will be similar ", to inverted CLKX1. If LEN is set to "0", its waveform will be similar to inverted CLKX2. In third format, DVALID signal also changes by LEN setting. DVALID signal and VCLK signal don't have any hazard pulse. Both DVALID and VCLK can be used as clock pulse. If CNTL656(Reg0x19[3]) is set to "0" in down scaling mode, TW9903 outputs Y invalid data as 0x10 and CbCr invalid data as 0x80 during HACTIVE active time. If CNTL656 is set to "1" in down scaling mode, TW9903 outputs Y invalid data 0x00 and CbCr invalid data 0x00. In 8-bit output mode, the CbCr invalid data is output first and then Y invalid data. TW9903 outputs only even number invalid data in invalid period during HACTIVE active time. TW9903 always outputs CbCr and Y 2-byte pair format data as valid data or invalid data.
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TW9903
These are illustrated in Figure 11a, 11b, 11c, 11d, 11e, and 11f.
CLKX2 DVALID VCLK VD[15:8]
invalid Cb0 Y0 Cr0 Y1 invalid Cb2 Y2 invalid Cr2 Y3 invalid
Figure 11a. 8-bit DVALID first format timing
CLKX2 DVALID VCLK VD[15:8]
invalid Cb0 Y0 Cr0 Y1 invalid Cb2 Y2 invalid Cr2 Y3 invalid
Figure 11b. 8-bit DVALID second format timing
CLKX2 DVALID VCLK VD[15:8]
invalid Cb0 Y0 Cr0 Y1 invalid Cb2 Y2 invalid Cr2 Y3 invalid
Figure 11c. 8-bit DVALID third format timing
CLKX1 DVALID VCLK VD[15:8] VD[7:0]
invalid Y0 Y1 invalid Y2 invalid Y3 invalid
invalid
Cb0
Cr0
invalid
Cb2
invalid
Cr2
invalid
Figure 11d. 16-bit DVALID first format timing
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TW9903
CLKX1 DVALID VCLK VD[15:8] VD[7:0]
invalid Y0 Y1 invalid Y2 invalid Y3 invalid
invalid
Cb0
Cr0
invalid
Cb2
invalid
Cr2
invalid
Figure 11e. 16-bit DVALID second format timing
CLKX1 DVALID VCLK VD[15:8] VD[7:0]
invalid Y0 Y1 invalid Y2 invalid Y3
invalid
Cb0
Cr0
invalid
Cb2
invalid
Cr2
Figure 11f. 16-bit DVALID third format timing CbCr data and CBFLAG In 8 output mode, TW9903 always outputs CbCr data when CLKX1 is high in video HACTIVE -bit active time as illustrated in Figure 3a. Even if TW9903 outputs H scaling down active pixel, CbCr data will be output when CLKX1 is high. Because TW9903 always outputs 2-byte pair format data on both valid pixel time and invalid pixel time. TW9903 outputs Cb data as the first valid CbCr data during video HACTIVE active time in 8-bit output mode. In 16-bit output mode, TW9903 outputs Cb data as the first valid CbCr data on VD[7:0] pins in video HACTIVE active time.TW9903 also has the optional CBFLAG signal. If CBFLAG is high during both DVALID and video HACTIVE active time, CbCr data is Cb data. If CBFLAG is low, then CbCr data is Cr data. Figure 12a shows 8-bit output mode CBFLAG timing. Figure 12b shows 16-bit output mode CBFLAG timing.
CLKX2 DVALID CBFLAG
Cb0 Cr0 Cb2 Cr2
Figure 12a. 8-bit output mode CBFLAG timing
CLKX1 DVALID CBFLAG
Cb0 Cr0 Cb2 Cr2
Figure 12b. 16-bit output mode CBFLAG timing
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TW9903
CLKX2 and CLKX1 CLKX2 is the delayed and buffered XTI clock signal. CLKX1 is 1/2 frequency clock signal of CLKX2. VCLK clock output is generally used as data strobing clock for down stream device with DVALID register setting as (Reg0x03[5:4]=01 or 10). ITU-R BT.656 If MODE(Reg0x03[7]) is set to "1" , TW9903 outputs ITU-R BT.656 compatible data on VD[15:8] in 8-bit output mode and on VD[15:0] in 16-bit output mode. All of control signals, sync signals, and clock signals have the same timing regardless of MODE bit setting. Only VD[15:8] or VD[15:0] video data changes. If MODE bit is set to "1",All data between EAV code and SAV code are filled by 0x80 for CbCr data and 0x10 for Y data. If MODE is set to "1", this blanking data and SAV/EAV code are the only difference from CCIR601 mode(MODE=0). TW9903 doesn output SAV/EAV code if the line doesn 't 't have HACTIVE signal. SAV code is generated on 4 CLKX2 clock timing before the leading edge of HACTIVE. EAV code is generated on 4 CLKX2 clock timing after the trailing edge of HACTIVE. 8-bit output mode is normally used in ITU-R BT.656 mode. But even if TW9903 is in 16-bit output mode, if MODE is set to "1", TW9903 output 4 bytes SAV/EAV code on VD[15:0] pins and the rest of HACTIVE non active period will be filled by Y 0x10 data and CbCr 0x80 data optionally. The changing timing of F bit and V bit in forth byte of SAV/EAV code are decided by VDELAY and VACTIVE register setting. EAV code will change before SAV code changes to maintain the compatibility with ITU-R BT.656 standard. Forth byte of SAV/EAV code is comprised of the following 8 bytes eventually. ITU-R BT.656 sequence is consisted of the following one by (a)-(b)-(c)-(d)-(e)-(f)-(a)-(b)- ... ... . If VIPCFG register bit is set to "1", MSB bit 7 of forth byte of SAV/EAV code is changed to "0" for special application.
EAV (a) (b) (c) (d) (e) (f) 0xB6 0x9D 0xB6 0xF1 0xDA 0xF1
SAV 0xAB 0x80 0xAB 0xEC 0xC7 0xEC Odd field V Blanking Line Odd field Active Video Line Odd field V Blanking Line Even field V Blanking Line Even field Active Video Line Even field V Blanking Line
The output timing is illustrated in Figure 13a,13b. The SAV and EAV sequences are shown in Table 3.
CLKX2 CLKX1 DVALID HACTIVE VD[15:8]
FF 00 00 XY 80 10 80 10 FF 00 00 XY
EAV
SAV
Figure 13a. 8-bit output mode ITU-R BT.656 Compatible Output timing
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TW9903
CLKX1 DVALID HACTIVE VD[15:8] VD[7:0]
00 XY 10 00 XY
FF
00
80
FF
00
EAV
SAV
Figure 13b.Optional 16-bit output with ITU-R BT.656 control code
First byte Second byte Third byte Forth byte
VD1 5 1 0 0 *C
Table 3. ITU-R BT.656 SAV and EAV code sequence VD1 4 VD13 VD12 VD11 VD10 VD9 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 F V H V XOR H F XOR H F XOR V
V = 1 - blanking, 0 - elsewhere
VD8 1 0 0 F XOR V XOR H
H = 0 - SAV, 1 - EAV
F = 0 - field 1, 1 - field 2
*C is set by VIPCFG register bit. Down-scaling and Cropping The TW9903 provides two methods to reduc e the amount of output video pixel data, downscaling and cropping. The downscaling provides full video image at lower resolution. Cropping provides only a portion of the video image output. All these mechanisms can be controlled independently to yield maximum flexibility in the output stream. TW9903 Down -Scaling The TW9903 can independently reduce the output video image size in both horizontal and vertical directions using arbitrary scaling ratios up to 1/16 in each direction. The horizontal scaling employs a dynamic 6 -tap 32-phase interpolation filter for luma and a 2 -tap 8-phase interpolation filter for chroma because of the limited bandwidth of the chroma data. The vertical scaling uses 2-tap to 5tap 8-phase interpolation filter dynamically for luma depending on the horizontal and vertical scaling ratio. Besides its normal scaling function, the scaling logic can be doubled as additional line comb filter to either reduce crawling dot or cross color at the expense or resolution. Downscaling is achieved by programming the horizontal scaling ratio register (HSCALE) and vertical scaling ratio register (VSCALE). When outputting unscaled video, the TW9903 will output CCIR601 compatible 720 pixels per line or any number of pixels per line as specified by the HACTIVE register. The standard output for Square Pixel mode is 640 pixels for 60 Hz system and 768 pixels for 50 Hz systems. If the number of output pixels required is smaller than 720 in CCIR601 compatible mode or the number specified by the HACTIVE register. The 12-bit HSCALE register, which is the concatenation of two 8-bit registers SCALE_HI and HSCALE_LO, is used to reduce the output pixels to the desired number.
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TW9903
Following is an example using pixel ratio to determine the horizontal scaling ratio. These equations should be used to determine the scaling ratio to be written into the 12-bit HSCALE register assuming HACTIVE is programmed with 720 active pixels per line: NTSC: PAL: Where: HSCALE = [720/Npixel_desired] * 256 HSCALE = [(720/N pixel_desired) ] * 256 Npixel_desired is the nominal number of pixel per line.
For example, to output a CCIR601 compatible NTSC stream at SIF resolution, the HSCALE value can be found as: HSCALE = [(720/320)] * 256 = 576 = 0x0240 However, to output a SQ compatible NTSC stream at SIF resolution, the HSCALE value should be found as: HSCALE = [(640/320)] * 256 = 512 = 0x200 In this case, with total resolution of 768 per line, the HACTIVE should have a value of 640. The vertical scaling determines the number of vertical lines output by the TW9903. The vertical scaling register (VSCALE) is a 12-bit register, which is the concatenation of a 4-bit register SCALE_HI and an 8 register VSCALE_LO. The maximum scaling ratio is 16:1. Following -bit equations should be used to determine the scaling ratio to be written into the 12-bit VSCALE register assuming VACTIVE is programmed with 240 or 288 active lines per field. 60Hz system: 50Hz system: VSCALE = [240/ Nline_desired] * 256 VSCALE = [288/ Nline_desired] * 256
Where: Nline_desired is the number of active lines output per field. The scaling ratios for some popular formats are listed in Table 4. TW9903 Cropping Cropping allows only subsection of a video image to be output. The VACTIVE signal can be programmed to indicate the number of active lines to be displayed in a video field, and the HACTIVE signal can be programmed to indicate the number of active pixels to be displayed in a video line. The start of the field or frame in the vertical direction is indicated by the leading edge of VSYNC. The start of the line in the horizontal direction is indicated by the leading edge of the HSYNC. The start of the active lines from vertical sync edge is indicated by the VDELAY register. The start of the active pixels from the horizontal edge is indicated by the HDELAY register. The sizes and location of the active video are determined by HDELAY, HACTIVE, VDELAY, and VACTIVE registers. These registers are 8-bit wide, the lower 8-bits is, respectively, in HDELAY_LO, HACTIVE_LO, VDELAY_LO, and VACTIVE_LO. Their upper 2-bit shares the same register CROP_HI. The Horizontal delay register (HDELAY) determines the number of pixels delay between the leading edge of HSYNC and the leading edge of the HACTIVE. Note that this value is referenced to the unscaled pixel number. The Horizontal active register (HACTIVE) determines the number of active pixels to be output or scaled after the delay from the sync edge is met. This value is also referenced to the unscaled pixel number. Therefore, if the scaling ratio is changed, the active video region used for scaling remain unchanged as set by the HACTIVE register, but the valid pixels output are equal or reduced due to down scaling. In order for the cropping to work properly, the following equation should be satisfied.
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TW9903
HDELAY + HACTIVE < Total number of pixels per line. For NTSC output at 13.5 MHz pixel rate, the total number of pixels is 858. The HDELAY should be set to 106 and HACTIVE set to 720. For PAL output at 13.5 MHz rate, the total number of pixels is 864. The HDELAY should be set to 108 and HACTIVE set to 720. The Vertical delay register (VDELAY) determines the number of lines delay between the leading edge of the VSYNC and the start of the active video lines. It indicates number of lines to skip at the start of a frame before asserting the VACTIVE signal. This value is referenced to the incoming scan lines before the vertical scaling. The number of scan lines is 525 for the 60Hz systems and 625 for the 50Hz systems. The Vertical active register (VACTIVE) determines the number of lines to be used in the vertical scaling. Therefore, the number of scan lines output is equal or less than the value set in this register depending on the vertical scaling ratio. In order for the vertical cropping to work properly, the following equation should be observed. VDELAY + VACTIVE < Total number of lines per field Table 4 shows some popular video formats and its recommended register settings. The CCIR601 format refers to the sampling rate of 13.5 MHz. The SQ format for 60 Hz system refers to the sampling rate of 12.27 MHz, and the SQ format for 50 Hz system refers to the use of sampling rate of 14.75 MHz.
Scaling Ratio
Format
Total Resolution 780x525 858x525 944x625 864x625 390x262 429x262 472x312 432x312 195x131 214x131 236x156 216x156
Output Resolution 640x480 720x480 768x576 720x576 320x240 360x240 384x288 360x288 160x120 180x120 192x144 180x144
HSCALE values 0x0100 0x0100 0x0100 0x0100 0x0200 0x0200 0x0200 0x0200 0x0400 0x0400 0x0400 0x0400
VSCALE (frame) 0x0100 0x0100 0x0100 0x0100 0x0200 0x0200 0x0200 0x0200 0x0400 0x0400 0x0400 0x0400
1:1
2:1 (CIF)
4:1 (QCIF)
NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601 NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601 NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601
Table 4. HSCALE and VSCALE value for some popular video formats.
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TW9903 VBI Data Processing
A frame of video is composed of 525 lines for NSTC and 625 for PAL. The time required for the electron beam to move from the bottom to the top of the screen is the vertical blanking period, and it requires the equivalent of 21 horizontal active video scan lines. This portion is normally not seen. During vertical blanking period, video lines before VBI Data are used for equalizing and synchronization. In 525 line video system, many TV channels have special VBI data from line 10 to line 21 or line22 in both odd and even fields. In 625 line video system, many TV channels have VBI data from line 6 or 7 to line 23 in both odd and even fields. They are normally regarded as the Vertical Blanking Interval or VBI portion of the video signal. TW9903 VBI Overview In the default configuration of the TW9903, the VBI region of the video signal is treated the same way as the real image signal. It will decode this region of signal as if it was video by Y/C separation and horizontal scaling. The TW9903 can also be configured in a mode known as VBI raw data mode. In this mode, the raw VBI region data (AD converter output data of input VIDEO signal) can be captured for later processing by software. It is done as follows. First, the analog composite video signal is digitized. Then, it is converted to 8 data stream at the input clock frequency, -bit normally 27MHz for a 27MHz crystal. Finally, the data is output to the VD [15:8] data pins in 8-bit output mode. It can also be output as a 16-bit data stream on pins VD [15:0] at half of the crystal rate in 16-bit output mode. There are three modes of operation for the VBI raw data output feature.
1) If VBI EN(Reg0x19[7]) is set to "0". VBI raw data output mode is disabled. This is the default
mode of operation. In this mode, the decoder doesn't output valid data on VBI lines.
2) If VBI EN(Reg0x19[7]) is set to "1", VBI raw data output mode is enabled.TW9903 outputs a
clock rate VBI data stream during VBI data lines from line 6 (in 625 line video system) or line10 (in 525 line video system) to the leading edge of VACTIVE. If LVALID is high and VACTIVE is low, the line is VBI data output line. When VACTIVE is high, the TW9903 outputs normal YCbCr data. Therefore, this mode can be used to capture both VBI raw data and normal YCbCr video data simultaneously.
3) If VBI Frame mode (Reg0x19[5]) is set to "1", VBI frame output mode is enabled. VBI Frame
mode bit has the higher priority than VBI EN bit. In this mode, TW9903 treats every scan line of the signal as a vertical interval line and outputs clock rate raw data on every line. Therefore, no video image data is output. This mode can be used to capture raw data for later processing. This mode of operation is designed for use in still-frame capture/processing applications. When the device is set to VBI raw data output mode, the VBI data is output during HACTIVE signal period. The DVALID or gated VCLK are used to indicate valid VBI data as in the normal video data output mode . A video/graphic cont roller should be able to do the following to capture VBI data output. It should keep track of the line count in order to select specific lines for VBI data processing. It must be able to use DVALID or VCLK for data qualification, and load only the valid data.
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TW9903
VBI Frame Output Mode In VBI frame output mode the TW9903 is generating VBI data all the time (i.e., there is no VBI active interval). In essence, the TW9903 is acting as an ADC continuously sampling the entire video signal at the crystal rate. The TW9903 generates HSYNC, VSYNC and FIELD timing signals in addition to the VBI data, but the DVALID, HACTIVE, and VACTIVE signals are all held high during VBI frame output operation. The behavior of the HSYNC, VSYNC, and FIELD timing signals is the same as n ormal YCbCr 4:2:2 output operation. The HSYNC, VSYNC, and FIELD timing signals are used by the video processor to detect the beginning of a video frame/field, at which point it can start to capture a full frame/field of VBI data.
VBI Byte Order In 8-bit output mode, if VBI Byte Order (Reg0x19[6]) is set to "0", 8-bit VBI output data have the following order. VBI2-VBI1-VBI4-VBI3-VBI6-VBI5- ... ... . Even number VBI data is output at first and odd number VBI data is output next. This function is useful for Motorola type CPU or similar logic. If VBI Byte Order (0x19[6]) is set to "1", 8-bit VBI output data have the following order. VBI1-VBI2-VBI3-VBI4-VBI5-VBI6- ... ... . . Odd number VBI data is output at first and even number VBI data is output next. This function is useful for Intel type CPU or similar logic. In 16-bit output mode, if VBI Byte Order (Reg0x19[6]) is set to "0", above odd number VBI data is output on VD[15:8] pins and even number VBI data is output on VD[7:0] pins. If VBI Byte Order (Reg0x19[6]) is set to "1", above even number VBI data is output on VD[15:8] pins and odd number VBI data is output on VD[7:0] pins.
Closed Captioning and Extended Data Services
Clock run-in
Frame code
2-byte character data
Figure 14. Typical CC/EDS scan line waveform
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TW9903
Line 21 Closed Captioning and line 284 Extended Data Service of 525-line video system is at a 0.5035MHz bit rate. Line 22, line 335 Closed Captioning of 625-line video system is at about 0.500MHz.It contains 14bits Clock Run-in by double bit rate, 3bits Start Bits, and 2 bytes data. Each of these 2 bytes is a 7 bit + odd parity ASCII character which represents text or control characters for positioning or display control. For the purposes of CC or EDS, only the Y component of the video signal is used. The TW9903 can be programmed to decode CC or EDS data by setting register 0x1A. Since the CC and EDS are independent, there could be one or both in a particular frame. A typical waveform is shown in Figure 14. CC/EDS decoder uses the internal low pass filtered VBI data with ADC sampling rate. CC/EDS Bit rate frequency is generated internally. In the CC/EDS decode mode, the decoder monitors the appropriate scan lines looking for the clock run-in and start bits pattern. If it s found, it starts tracking Clock Run-in Frequency and checks the ' status of Clock Run-in and start bits. Some programming may use these s can lines for other purpose. The caption data is sampled and loaded into shift registers, and the data is then transferred to the caption data FIFO. The TW9903 provides a 16 x 10 location FIFO for storing CC/EDS data. Once the video decoder detects the correct status of Clock Run-in, Start Bits in the CC/EDS signal, it captures the low byte of CC/EDS data at first and high byte next. Data is stored in the FIFO low byte first and high byte next sequentially. Captioned data is available to the user through the CC_DATA register (0x1B). Upon being placed in the 10-bit FIFO, two additional bits are attached to the CC/EDS data byte by TW9903's CC/EDS decoder. These two bits indicate whether the given byte stored in the FIFO corresponds to CC or EDS data and whether it is the high or low byte of CC/EDS. These two bits are available to the user through the CC_STATUS register bits CC_EDS and LO_HI (0x1A[1:0]), respectively. As stored in the FIFO, LO_HI is bit 8 and CC_EDS is bit 9. Additionally, the TW9903 reports the results of the parity check in the PARITY bit in the CC_STATUS register. FIFO can hold 17 data Initially when the FIFO is empty, . bit FF_EMP in the CC_STATUS register (0x1A[2]) is set low indicating that no data is available in the FIFO. Subsequently, when data has been stored in the FIFO, the FF_EMP bit is set to logical high. Once the FIFO has more than 8 bytes, the CC_VALID pin outputs low if CCVALID_EN bit in CC_STATUS register (0x1A[7]) is high and CCVALID bit in CSTATUS register(0x01[2]) also becomes high. If CC_VALID pin is used, CCVALID pin must have external pull-up resister of 4.75 ...10kohm typically. While FIFO has less than 7data, if CCVALID_EN bit is disabled (0x1A[7]=0), CCVALID pin always outputs high by external pull-up resister. If there is no pull-up resister, CVALID pin outputs tri-state unstable signal. CCVALID pin is used when hardware handshaking with Micro controller is needed. In many applications, only CCVALID bit in CSTATUS register(0x01[2]) is used normally. If the FIFO read cycle time is long, then FIFO overflow condition may happen. After 17 data are stored in FIFO, FF_OVF bit in CC_STATUS register(0x1A[3]) becomes high. After FF_OVF becomes high, any incoming data causes only 17th location data to be overwritten. After FIFO is read and FIFO has less than 16 data, FF_OVF bit becomes low. However, once FF_OVF bit becomes high some data loss may happen. In this case, FIFO must be reset by the following way (a) or (b). Method (b) is most often used. (a) Execute Software Reset (Write 0x06[7]=1) (b) Write CC_STATUS register bits 0x1A[6:5]=00 16 times read CC_DATA register 0x1B continuously Write CC_STATUS Register bits 0x1A[6:5] for the application again There will routinely be asynchronous reads and writes to the CC/EDS FIFO. The writes will be from the CC/EDS circuitry and the reads will occur as the system controller reads the CC/EDS data from TW9903. These reads and writes will not occur until FIFO is in overflow condition. The average FIFO Read cycle time must be shorter than Closed Captioning byte transmitter cycle time. If either odd field Close Captioning or even field Closed Captioning is enabled, the average FIFO read cycle time must be shorter than 2 times write per 1 frame cycle. If both odd field Closed Captioning
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TW9903
and even field Closed Captioning are enabled, it must be shorter than 4 times write per 1 frame cycle. Otherwise, FIFO will be in overflow condition theoretically. Typical FIFO Read flows are as follows. These flows are written similar to C language type. Case 1 : typical I2C Master with normal read cycle speed CONT1: Write CC_STATUS register bits 0x1A[6:5]=00 Read 16 times CC_DATA register 0x1B Write CC_STATUS register bits 0x1A[6:5] for the application CONT2: Read CC_STATUS register 0x1A If(FF_OVF bit==1) goto CONT1 else if(FF_EMP bit ==0) goto CONT2 or goto CONT3 else { if(PARITY bit==1) { read CC_DATA register 0x1B Abandon this CC_DATA goto CONT2 or goto CONT3 } else { Check CC_EDS bit and store field information read CC_DATA register 0x1B(store 1 data) } } CONT3: execute another program routine goto CONT2 Case2 : Too slow speed I2C Master or program with too big waiting time to cause overflow often. CC_STATUS Register bits 0x1A[6:5]=01 or10. CONT4: Write CC_STATUS register bits 0x1A[6:5]=00 Read 16 times CC_DATA register 0x1B Write CC_STATUS register bits 0x1A[6:5] for the application CONT5: Read CSTATUS register 0x01 If(CCVALID bit==0) goto CONT5 or goto CONT6 Read CC_STATUS register If(FF_OVF bit ==1) goto CONT4 Read 8times CC_DATA register 0x1B(Store 8 data) while (1) { Read CC_STATUS Register 0x1A If(FF_EMP bit==0) break or goto CONT6 else Read 0x1B (store1 data) continue } CONT6: execute another program routine goto CONT5
Two Wire Serial Bus Interface
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Start Condition SDA
Stop Condition
SCL
Figure 15. Definition of the serial bus interface bus start and stop
Figure 16. One complete register read sequence via the serial bus interface
Device ID (1-7) R/W Index (1-8)
SDAT SCLK Start Condition Ack Ack
Device ID (1-7)
R/W
Data (1-8)
Re-start Condition
Ack
Stop Ack Condition
Device ID (1-7)
R/W
Index (1-8)
Data (1-8)
SDAT SCLK Start Condition Ack Ack Ack Stop Condition
Figure 17. One complete register write sequence via the serial bus interface
The two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the TW9903 registers. SCLK is the serial clock and
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SDAT is the data line. Both lines are pulled high by resistors connected to VDD. ICs communicate on the bus by pulling SCLK and SDAT low through open drain outputs. In normal operation the master generates all clock pulses, but control of the SDAT line alternates back and forth between the master and the slave. For both read and write, each byte is transferred MSB first, and the data bit is valid whenever SCLK is high. The TW9903 is operated as a bus slave device. It can be programmed to respond to one of two 7bit slave device addresses by tying the SIAD (Serial Interface ADdress) pin ether to VDD or GND (See Table 5.). If the SIAD pin is tied to VDD, then the least significant bit of the 7-bit address is a "1". If the SIAD pin is tied to GND then the least significant bit of the 7-bit address is a "0". The most significant 6-bits are fixed. The 7-bit address field is concatenated with the read/write control bit to form the first byte transferred during a new transfer. If the read/write control bit is high the next byte will be read from the slave device. If it is low the next byte will be a write to the slave. When a bus master (the host microprocessor) drives SDA from high to low, while SCL is high, this is defined to be a start condition (See Figure 15.). All slaves on the bus listen to determine when a start condition has been asserted. After a start condition, all slave devices listen for the their device addresses. The host then sends a byte consisting of the 7 slave device ID and the R/W bit. This is shown in Figure 16. (For the -bit TW9903, the next byte is normally the index to the TW9903 registers and is a write to the TW9903 therefore the first R/W bit is normally low.) After transmitting the device address and the R/W bit, the master must release the SDAT line while holding SCLK low, and wait for an acknowledgement from the slave. If the address matches the device address of a slave, the slave will respond by driving the SDAT line low to acknowledge the condition. The master will then continue with the next 8-bit transfer. If no device on the bus responds, the master transmits a stop condition and ends the cycle. Notice that a successful transfer always includes nine clock pulses. To write to the internal register of theTW9903, the master sends another 8 -bits of data, the TW9903 loads this to the register pointed by the internal index register. The TW9903 will acknowledge the 8 data transfer and automatically increment the index in preparation for the -bit next data. The master can do multiple writes to the TW9903 if they are in ascending sequential order. After each 8 transfer the TW9903 will acknowledge the receipt of the 8 -bit -bits with an acknowledge pulse. To end all transfers to the TW9903 the host will issue a stop condition. Serial Bus Interface 7-bit Slave Address 1 0 0 0 1 SIAD1 SIAD0 Read/Write bit 1=Read 0=Write
Table 5 TW9903 serial bus interface 7-bit slave address and read write bit A TW9903 read cycle has two phases. The first phase is a write to the internal index register. The second phase is the read from the data register. (See figure 16). The host initiates the first phase by sending the start condition. It then sends the slave device ID together with a 0 in the R/W bit position. The index is then sent followed by either a stop condition or a second start condition. The second phase starts with the second start condition. The master then resends the same slave device ID with a 1 in the R/W bit position to indicate a read. The slave will transfer the contents of the desired register. The master remains in control of the clock. After transferring eight bits, the slave releases and the master takes control of the SDAT line and acknowledges the receipt of data to the slave. To terminate the last transfer the master will issue a negative acknowledge (SDAT is left high during a clock pulse) and issue a stop condition.
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TW9903 Test Modes
The test mode is provided by the TMODE input pin. If this pin is de-asserted (low), the TW9903 is in its normal operating mode. When this pin is asserted (high), the TW9903 is in test mode, and the mode is controlled by TEST1 and TEST2 input pins as shown in Table 6. Table 6. Test mode selection and description Test mode Reserved Pin tri-state TEST2 0 0 TEST1 0 1 In this mode, all pin output drivers are tri-stated. Pin leakage current parameters can be measured. In this mode, all pin output drivers are forced to the high output state. Pin output high voltage, VOH and IOH, can be measured. In this mode, all pin output drivers are forced to the low output state. Pin output high voltage, VOL and IOL, can be measured. Description
Outputs high
1
0
Outputs low
1
1
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TW9903 Filter Curves
Decimation filter
0
-5
Magnitude Response (dB)
-10
-15
-20
-25
-30
-35
-40 0 2 4 6 8 10 12 14 x 10
6
Frequency (Hertz)
Chroma Band Pass Filter Curves
0
-5
-10
Magnitude Response (dB)
-15
-20
PAL/SECAM NTSC
-25
-30
-35
-40
-45
-50 0 1 2 3 4 5 6 7 8 x 10 9
6
Frequency (Hertz)
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Luma Notch Filter Curve for NTSC and PAL/SECAM
0
-10
Magnitude Response (dB)
-20
PAL/SECAM
-30
NTSC
-40
-50
-60
-70
-80 0 1 2 3 4 5 6 7 8 x 10 9
6
Frequency (Hertz)
Chrominance Low-Pass Filter Curve
0
-5
CBW=3
-10 -15
CBW=2 CBW=1
-20
Gain (dB)
CBW=0 Low
High
-25 -30
Med
-35 -40 -45 -50 0 1 2 3 Frequency (Hertz) 4 5 x 10 6
6
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Horizontal Scaler Pre- Filter curves
0
-5
Magnitude Response (dB)
High
-10
Low
-15
HFLT[1:0]=1 HFLT[1:0]=2 Med
-20
HFLT[1:0]=3
-25
-30
-35
-40 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Fsig/Fsample
Vertical Interpolation Filter curves
0
-5
Magnitude Response (dB)
-10
-15
-20
-25
-30 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Fv / Line Rate
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Peaking Filter Curves NTSC
16
14
Magnitude Response (dB)
12
10
8
6
4
2
0 0 1 2 3 4 5 6 x 10 7
6
Frequency (Hertz)
PAL
16
14
Magnitude Response (dB)
12
10
8
6
4
2
0 0 1 2 3 4 5 6 7 8 x 10 9
6
Frequency (Hertz)
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Control Register
TW9903 Register SUMMARY
Index (HEX)
7
6
5
ID
4
3
2
1
REV
0
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
VDLOSS * MODE * LVALID_ POL
HLOCK FC27 LEN * DVALID_ POL
SLOCK FIELD IFSEL DVALID VACTIVE _POL CBFLAG _POL
VLOCK CCVALID YSEL VSCTL FIELD_P OL OEN HSDLY HACTIVE _POL
MONO CSEL
DET50 SEL
TRI_SEL HSYNC_ POL VSYNC_ POL
Reset value 19h 00h 40h 04h 00h 00h 03h 02h 13h F0h 78h D0h 8Ch 00h 11h 00h 00h 60h 01h 7Fh 5Ah 00h C3h 80h 44h 58h 80h X 00h 00h X0h 00h
SRESET IREF VDELAY_HI
VREF AGC_EN VACTIVE_HI
CLKPDN Y_PDN HDELAY_HI
C_PDN * HACTIVE_HI
VDELAY_LO VACTIVE_LO HDELAY_LO HACTIVE_LO PBW DEM PALSW SET7 COMB VSC ALE_LO HSCALE_LO BRIGHTNESS CONTRAST SCURVE * * SAT_U SAT_V HUE SHLMT * * VBI_EN CCVALID _EN DTSTUS START VBI_BYT EDS_EN CCOR VBI_FM CC_EN HA_EN PARITY CTL656 FF_OVF * FF_EMP SHCOR * BKCOR RTSEL CC_EDS LO_HI SHARPNESS HCOMP YCOMB CCOMB
VSCALE_HI
HSCALE_HI
CC_DATA PAL60 IN TEST STDNOW PALCN PALM ATREG NTSC4 SECAM STANDARD PALB NTSC
OUT
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Index (HEX)
7
6
CLPEND NMGAIN
5
4
3
2
CLPST WPGAIN
1
0
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B
Agcgain8
CLMPLD SYNCTD MISSCNT VLCKI BSHT CKILMAX HTL CKLM EVCNT HPM NKILL sf CTEST PKILL pf YCLEN SKILL ff CCLEN YDLY HFLT ACCT VLCKO
AGCGAIN[7:0] PEAKWT CLMPL SYNCT HSWIN PCLAMP VMODE DETV AFLD VINT
CCEVENLINE(VSHT) CKILMIN VTL TBC_EN CBAL FCS HSLEN BYPASS SYOUT CBW LCS CCS CSTRIPE CKLY BST CTYPE CKLC HADV
SPM
VBILPF NODTEN ANCEN CRCERR * * SYRM TOUTHA WSSFLD * * WKAIR * WSSEN VIPCFG
kf CSBAD MCVSN VCLEN GTEST VLPF FILLDATA SDID DID CCODDLINE SLICELEVEL WSS[13:8] WSS[7:0] VSTD NINTL HREF * CLMD WSSDET
EDSDET PSP
CCDET
Reset value A0h 22h F0h FEh 3Ch 38h 44h 20h 00h 15h A0h 44h 38h 00h A5h E0h 00h 00h A0h 22h 11h 35h 72h X X 0 x 5
0x00 - Product ID Code Register (ID) Bit 7-3 2-0 Function ID Revision R/W R R Description The TW9903 Product ID code is 00011. The revision number. Reset 03h 1
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0x01 - Chip Status Register (CSTATUS) Bit 7 Function VDLOSS R/W R Description 1 = Video not present. (sync is not detected in number of consecutive line periods specified by Misscnt register) 0 = Video detected. 6 HLOCK R 1 = Horizontal sync PLL is locked to the incoming video source. 0 = Horizontal sync PLL is not locked. 5 SLOCK R 1 = Sub-carrier PLL is locked to the incoming video source. 0 = Sub-carrier PLL is not locked. 4 FIELD R 0 = Odd field is being decoded. 1 = Even field is being decoded. 3 VLOCK R 1 = Vertical logic is locked to the incoming video source. 0 = Vertical logic is not locked. 2 CCVALID R This bit indicates that valid closed caption or extended data service data pairs have been stored in the CC_DATA register and the FIFO is half full. 1 = No color burst signal detected. 0 = Color burst signal detected. 0 DET50 R 0 = 60Hz source detected 1 = 50Hz source detected The actual vertical scanning frequency depends on the current standard invoked. 0 0 0 0 0 0 Reset 0
1
MONO
R
0
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0x02 - Input Format (INFORM) Bit 7 6 Function Reserved FC27 R/W 1 = Input crystal clock frequency is 27MHz. 0 = Square pixel mode. Must use 24.54MHz for 60Hz field rate source or 29.5MHz for 50Hz field rate source. 5-4 IFSEL R/W 10 = Component video decoding 01 = S-video decoding 00 = Composite video decoding 3-2 YSEL R/W These two bits control the input video selection. It selects between all composites source, or three composites and one S-video source. 00 = Route MUX0 input to MXOUT 01 = Route MUX1 input to MXOUT 10 = Route MUX2 input to MXOUT 11 = Route MUX3 input to MXOUT 1 CSEL R/W This bit selects the chroma channel input. 0 = C_PBIN0 1 = C_PBIN1 0 SEL R/W This bit determine the method of Y input MUX control 0 = by YSEL 1 = by pin SEL1, SEL0 0 0 00 00 1 R/W Description Reset
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0x03 - Output Format Control Register (OPFORM) Bit 7 Function MODE R/W R/W Description 0 = CCIR601 compatible YCrCb 4:2:2 format with separate syncs and flags. 1 = ITU-R-656 compatible data sequence format. 6 LEN R/W 0 = 8-bit YCrCb 4:2:2 output format based on CLKX2. 1 = 16-bit YCrCb 4:2:2 output format based on CLKX1. 5-4 DVALID R/W 00 = DVALID is in the first format with VCLK used as data strobe. 01 = DVALID is in the second format with DVALID indicating the valid data period. 10 = DVALID is in the third format with DVALID used as data strobe. 3 VSCTL R/W 1 = Vertical scale-downed output controlled by DVALID only. 0 = Vertical scale-downed output controlled by both HACTIVE and DVALID. 2 OEN R/W 0 = Enable outputs. 1 = Tri-state outputs defined by Tri-state select bits of this register. 1-0 TRI_SEL R/W These bits select the outputs to be tri-stated when the OEN bit is asserted high. There are three major groups that can be independently tri-stated: timing group (HSYNC, VSYNC, HACTIVE, VACTIVE, CBFLAG, DVALID, MPOUT, FIELD), data group (VD[15:0]), and clock group (CLKX1, CLKX2, VCLK) according to following definition. If OE# pin is asserted high, all of these pins are tri-stated regardless of this setting. 00 = Timing and data group only. 01 = Data group only. 10 = All three groups. 11 = Clock and data group only. 00b 1 0 0 0 Reset 0
0x04 - GAMMA and HSYNC Delay Control Bit 7 6-5 4-0 Function Reserved Reserved HSDLY R/W R/W R/W RW These bits control the position of the HSYNC pin output relative to the internal reference in 4 CLKX1 step. 5h is recommended. Description Reset 0 0 0
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0x05 - Output Polarity Register (POLARITY) Bit 7 Function LVALID R/W R/W Description 0 = LVALID pin is active high. 1 = LVALID pin is active low. 6 DVALID R/W 0 = DVALID pin is active high. 1 = DVALID pin is active low. 5 VACTIVE R/W 0 = VACTIVE pin is active high. 1 = VACTIVE pin is active low. 4 CBFLAG R/W 0 = CBFLAG pin is active high. 1 = CBFLAG pin is active low. 3 FIELD R/W 0 = FIELD pin is low for the odd field. 1 = FIELD pin is low for the even field. 2 HACTIVE R/W 0 = HACTIVE pin active high. 1 = HACTIVE pin active low. 1 HSYNC R/W 0 = HSYNC pin active low. 1 = HSYNC pin active high. 0 VSYNC R/W 0 = VSYNC pin active low. 1 = VSYNC pin active high. 0 0 0 0 0 0 0 Reset 0
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0x06 - Analog Control Register (ACNTL) Bit 7 6 Function SRESET IREF R/W W R/W Description An 1 written to this bit resets the device to its default state but all register content remain unchanged. This bit is self-resetting. 0 = Internal current reference 1. 1 = Internal current reference 2. 5 VREF R/W 1 = Internal voltage reference. 0 = external voltage reference using VCOM, VREFP and VREFN. 4 AGC_EN R/W 0 = AGC loop function enabled. 1 = AGC loop function disabled. Gain is set to by AGCGAIN. 3 CLK_PDN R/W 0 = Normal clock operation. 1 = System clock in power down mode, but the MPU INTERFACE module and output clocks (CLKX1 and CLKX2) are still active. 2 Y_PDN R/W 0 = Luma ADC in normal operation. 1 = Luma ADC in power down mode. 1 C_PDN R/W 0 = Chroma ADC in normal operation. 1 = Chroma ADC in power down mode. 0 Reserved R/W 0 1 0 0 0 0 Reset 0 0
0x07 - Cropping Register, High (CROP_HI) Bit 7-6 Function VDELAY_ HI R/W R/W Description These bits are bit 9 to 8 of the 10-bit Vertical Delay register. Reset 0
5-4
VACTIVE_ R/W HI HDELAY_ HI HACTIVE _HI R/W
These bits are bit 9 to 8 of the 10-bit VACTIVE register. Refer to description on Reg09 for its shadow register. These bits are bit 9 to 8 of the 10-bit Horizontal Delay register.
0
3-2
0
1-0
R/W
These bits are bit 9 to 8 of the 10-bit HACTIVE register.
10b
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0x08 - Vertical Delay Register, Low (VDELAY_LO) Bit 7-0 Function VDELAY_ LO R/W R/W Description These bits are bit 7 to 0 of the 10-bit Vertical Delay register. The two MSBs are in the CROP_HI register. It defines the number of lines between the leading edge of VSYNC and the start of the active video. Reset 13h
0x09 - Vertical Active Register, Low (VACTIVE_LO) Bit 7-0 Function R/W Description These bits are bit 7 to 0 of the 10-bit Vertical Active register. The two MSBs are in the CROP_HI register. It defines the number of active video lines per frame output. The VACTIVE register has a shadow register for use with 50Hz source when Atreg of Reg0x1C is not set. This register can be accessed through the same index address by first changing the format standard to any 50Hz standard. Reset F0h
VACTIVE_ R/W LO
0x0A - Horizontal Delay Register, Low (HDELAY_LO) Bit 7-0 Function HDELAY_ LO R/W R/W Description These bits are bit 7 to 0 of the 10-bit Horizontal Delay register. The two MSBs are in the CROP_HI register. It defines the number of pixels between the leading edge of the HSYNC and the start of the image cropping for active video. The HDELAY_LO register has two shadow registers for use with PAL and SECAM sources respectively. These register can be accessed using the same index address by first changing the decoding format to the corresponding standard. Reset 78h
0x0B - Horizontal Active Register, Low (HACTIVE_LO) Bit 7-0 Function HACTIVE _LO R/W R/W Description These bits are bit 7 to 0 of the 10-bit Horizontal Active register. The two MSBs are in the CROP_HI register. It defines the number of active pixels per line output. Reset D0h
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0x0C - Control Register I (CNTRL1) Bit 7 Function PBW R/W R/W Description 1 = Wide Chroma BPF BW 0 = Normal Chroma BPF BW 6 5 DEM PALSW R/W R/W Slock sensitivity 1 = PAL switch sensitivity low. 0 = PAL switch sensitivity normal. 4 SET7 R/W 1 = The black level is 7.5 IRE above the blank level. 0 = The black level is the same as the blank level. 3 COMB R/W 1 = Adaptive comb filter on for NTSC 0 = Notch filter 2 HCOMP R/W 1 = operation mode 1. 0 = mode 0. 1 YCOMB R/W This bit controls the Y comb. 1 = Y output is the averaging of two adjacent lines. 0 = No comb. 0 CCOMB R/W This bit controls the UV comb. 1 = UV output is the averaging of two adjacent lines. 0 = No comb. 0 0 1 1 0 0 0 Reset 1
0x0D - Vertical Scaling Register, Low (VSCALE_LO) Bit 7-0 Function VSCALE_ LO R/W R/W Description These bits are bit 7 to 0 of the 12-bit vertical scaling ratio register Reset 00h
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0x0E - Scaling Register, High (SCALE_HI) Bit 7-4 Function VSCALE_ HI HSCALE_ HI R/W R/W Description These bits are bit 11 to 8 of the 12-bit vertical scaling ratio register. Reset 01h
3-0
R/W
These bits are bit 11 to 8 of the 12-bit horizontal scaling ratio register.
01h
0x0F - Horizontal Scaling Register, Low (HSCALE_LO) Bit 7-0 Function HSCALE_ LO R/W R/W Description These bits are bit 7 to 0 of the 12-bit horizontal scaling ratio register. Reset 00h
0x10 - BRIGHTNESS Control Register (BRIGHT) Bit 7-0 Function Brightness R/W R/W Description These bits control the brightness. They have value of -128 to 127 in 2's complement form. Positive value increases brightness. A value 0 has no effect on the data. Reset 00h
0x11 - CONTRAST Control Register (CONTRAST) Bit 7-0 Function Contrast R/W R/W Description These bits control the contrast. They have value of 0 to 3.98 (FFh). A value of 1 (100_0000) has no effect on the video data. Reset 60h
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0x12 - SHARPNESS Control Register I (SHARPNESS) Bit 7 Function SCURVE R/W R/W Description This bit controls the sharpness filter center frequency. 0 = Normal 6 5-4 3-0 Reserved Reserved SHARP R/W R/W R/W These bits control the amount of sharpness enhancement on the luminance signals. There are 16 levels of control with '0' having no effect on the output image. 1 through 7 provides sharpness enhancement with '7' being the strongest. Value 8 through 15 are provided for noise reduction purpose. 1 = High 0 0 1 Reset 0
0x13 - Chroma (U) Gain Register (SAT_U) Bit 7-0 Function SAT_U R/W R/W Description These bits control the digital gain adjustment to the U (or Cb) component of the digital video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can also be adjusted independently to provide greater flexibility. The range of adjustment is 0 to 200%. Reset 7Fh
0x14 - Chroma (V) Gain Register (SAT_V) Bit 7-0 Function SAT_V R/W R/W Description These bits control the digital gain adjustment to the V (or Cr) component of the digital video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can a be lso adjusted independently to provide greater flexibility. The range of adjustment is 0 to 200%. Reset 5Ah
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0x15 - Hue Control Register (HUE) Bit 7-0 Function HUE R/W R/W Description These bits control the color hue. They have value from +96 (7Fh) o o o to -96 (80h) with an increment of 0.75 . The default value is 0 (00h).
o
Reset 00h
0x16 - Sharpness Control Register II Bit 7-4 3-0 Function SHLMT SHCOR R/W R/W R/W Description These bits limit the maximum enhancement level regardless of the SHARP setting. The internal step size is 8. These bits provide coring function for the sharpness control. Reset C 3
0x17 - Reserved Bit 7-4 3-0 Function * * R/W R/W R/W Description Reset 0 0
0x18 - Coring Control Register (CORING) Bit 7-6 5-4 3-2 1-0 Function Reserved CCOR Reserved BKCOR R/W R/W R/W R/W R/W These bits control the black level coring function. These bits control the low level coring function for the Cb/Cr output. Description Reset 0 0h 0h 0h
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0x19 - VBI Control Register (VBICNTL) Bit 7 Function VBI EN R/W R/W 0 = VBI capture disabled. 1 = VBI capture enabled. 6 VBI Byte R/W Order If LEN(Reg0x03[6]) is "1" 0 = Pixel 1, 3, 5 ... on the VD[15:8] data bus, and pixel 2, 4, 6, ... on the VD[7:0] data bus. 1 = Pixel 1, 3, 5, ... on the VD[7:0] data bus, and pixel 2, 4, 6, ... on the VD[15:8] data bus. If LEN is "0" 0 = Pixel 2,1,4,3,6,5, ... . on the VD[15:8] data bus. 1 = Pixel 1,2,3,4,5,6, ... . on the VD[15:8] data bus. 5 VBI Frame Mode R/W 0 = VBI Frame output mode disabled. VBI capture is controlled by bit 7 of this register. 1 = VBI Frame output mode enabled. VBI capture is always enabled. 4 HA_EN R/W 0 = HACTIVE output is disabled during vertical blanking period. 1 = HACTIVE output is enabled during vertical blanking period. 3 CNTL656 R/W 0 = 0x80 and 0x10 code will be output as invalid data during active video line. 1 = 0x00 code will be output as invalid data during active video line. 2-0 RTSEL R/W These bits control the real time signal output from the MPOUT pin. 000 = Video loss 001 = H-lock 010 = S-lock 011 = V-lock 100 = MONO 101 = Det50 110 = Mcvsn 111 = LVALID 0 1 1 0 1 Description Reset 0
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0x1A - CC/EDS Status Register (CC_STATUS) Bit 7 Function CCVALID _EN EDS_EN R/W R/W Description 0 = Disable CCVALID interrupt pin. 1 = Enable CCVALID interrupt pin. R/W 0 = EDS data is not transferred to the CC_DATA fifo. 1 = EDS data is transferred to the CC_DATA fifo. 5 CC_EN R/W 0 = CC data is not transferred to the CC_DATA fifo. 1 = CC data is transferred to the CC_DATA fifo. 4 PARITY R 0 = Data in CC_DATA has no error. 1 = Data in CC_DATA has odd parity error. 3 FF_OVF R 0 = An overflow has not occurred. 1 = An overflow has occurred in the CC_DATA fifo. 2 FF_EMP R 0 = CC_DATA fifo is empty. 1 = CC_DATA fifo has data available. 1 CC_EDS R 0 = Closed caption data is in CC_DATA register. 1 = Extended data service data is in CC_DATA register. 0 LO_HI R 0 = Low byte of the 16-bit word is in the CC_DATA register. 1 = High byte of the 16-bit word is in the CC_DATA register. X X 0 0 X 0 0 Reset 1
6
0x1B - CC/EDS Data Register (CC_DATA) Bit 7-0 Function CC Data R/W R Description These bits store the incoming closed caption or even field closed caption data. Reset 80h
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TW9903
0x1C - Standard Selection (SDT) Bit 7 6-4 Function DETSTUS STDNOW R/W R R 0 = Idle Description 1 = detection in progress Reset 0 0
Current standard invoked 0 = NTSC(M) 1 = PAL (B,D,G,H,I) 2 = SECAM 3 = NTSC4.43 4 = PAL (M) 5 = PAL (CN) 6 = PAL 60 7 = Not valid
3
ATREG
R/W
1 = Disable the shadow registers. 0 = Enable VACTIVE and HDELAY shadow registers value depending on standard
0
2-0
Standard
R/W
Standard selection 0 = NTSC(M) 1 = PAL (B,D,G,H,I) 2 = SECAM 3 = NTSC4.43 4 = PAL (M) 5 = PAL (CN) 6 = PAL 60 7 = Auto detection
0h
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0x1D - Standard Recognition (SDTR) Bit 7 6 Function ATSTART R/W R/W R/W Description Writing 1 to this bit will manually initiate the auto format detection process. This bit is a self-resetting bit. 1 = enable recognition of PAL60. 0 = disable recognition. 5 R/W 1 = enable recognition of PAL (CN). 0 = disable recognition. 4 R/W 1 = enable recognition of PAL (M). 0 = disable recognition. 3 R/W 1 = enable recognition of NTSC 4.43. 0 = disable recognition. 2 R/W 1 = enable recognition of SECAM. 0 = disable recognition. 1 R/W 1 = enable recognition of PAL (B,D,G,H,I). 0 = disable recognition. 0 R/W 1 = enable recognition of NTSC (M). 0 = disable recognition. 0 0 0 0 0 0 Reset 0 0
0x1E - General Programmable I/O Register (GPIO) Bit 7-4 Function IN[3:0] R/W R Description These input bits can be used to monitor external signals from VD[7:4] while in 8-bit output mode (Length bit of OPFORM register equals 0). If not in the 8-bit output mode, the values of these bits are not valid. These output bits can be programmed to output additional signals on VD[3:0] while in 8 -bit output mode. If not in the 8-bit output mode, these bits have no effect on the pins. Reset X
3-0
OUT[3:0]
R/W
0h
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0x1F - Test Control Register (TEST) Bit 7-0 Function TEST R/W R/W Description This register is reserved for testing purpose. In normal operation, only 0 should be written into this register. 1 = Analog test mode. Y and C channel portion of the device can be tested in this mode. The Y channel ADC output can be obtained from HACTIVE, HSYNC and VD[15:8] for bit1, bit0 and bit9-2, respectively. The C channel ADC output can be obtained from VACTIVE, VSYNC and VD[7:0] for bit1, bit0 and bit9-2, respectively. 2 = Digital test mode1. The sync portion of the device should be tested in this mode. The 8-bit input corresponds to TISVN, TEST1, TEST2, TDO, TCK, TRST#, TMS, and TDI in the order of bit 7 to 0. 3 = Analog test mode 1. It is same as the previous analog test mode except that the C channel ADC inputs come from TADCP and TADCN instead of C_PBIN. 4 = Digital test mode 2. In addition to digital test mode 1, this test mode allows the C channel data to be inputted from VD[7:0]. In this mode, only 8-bit output format is allowed. 5 = Closed Caption test mode. 6 = Analog test mode 2. The "C channel portion of the device can be tested in this mode. The C channel ADC output can be obtained from VACTIVE, VSYNC and VD[7:0] for bit1, bit0 and bit9-2, respectively. 7 = Analog DAC output mode. The 6-bit Sync output corresponds to TDI, TMS, TRST#, TCK, TISVN and TDO in the order of bit 5 to 0. Y and Cb/Cr outputs correspond to VD[15:8] and VD[7:0], respectively. In this mode, HACTIVE pin will be BGOUT and VACTIVE pin will be VSDLY. Reset 0
0x20 - Clamping Gain (CLMPG) Bit 7-4 Function CLPEND R/W R/W Description These 4 bits set the end time of the clamping pulse in the increment of 8 system clocks. The clamping time is determined by this together with CLPST. These 4 bits set the start time of the clamping pulse in the increment of 8 system clocks. It is referenced to PCLAMP position. Reset A
3-0
CLPST
R/W
0
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0x21 - Individual AGC Gain (IAGC) Bit 7-4 3-1 0 Function NMGAIN WPGAIN AGCGAIN R/W R/W R/W R/W Description These bits control the normal AGC loop maximum correction value. Peak AGC loop gain control. This bit is the MSB of the 9-bit register that controls the AGC gain when AGC loop is disabled. Reset 2 1 0
0x22 - AGC Gain (AGCGAIN) Bit 7-0 Function AGCGAIN R/W R/W Description These bits are the lower 8 bits of the 9-bit register that controls the AGC gain when AGC loop is disabled. Reset F0h
0x23 - White Peak Threshold (PEAKWT) Bit 7-0 Function PEAKWT R/W R/W Description These bits control the white peak detection threshold. Reset FEh
0x24- Clamp level (CLMPL) Bit 7 Function CLMPLD R/W R/W Description 0 = Clamping level is set by CLMPL. 1 = Clamping level preset at 60d. 6-0 CLMPL R/W These bits determine the clamping level of the Y channel. 3Ch Reset 0
0x25- Sync Amplitude (SYNCT) Bit 7 Function SYNCTD R/W R/W Description 0 = Reference sync amplitude is set by SYNCT. 1 = Reference sync amplitude is preset to 38h. 6-0 SYNCT R/W These bits determine the standard sync pulse amplitude for AGC reference. 38h Reset 0
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0x26 - Sync Miss Count Register (MISSCNT) Bit 7-4 3-0 Function MISSCNT HSWIN R/W R/W R/W Description These bits set the thres hold for horizontal sync miss count threshold. These bits determine the Hsync detection window. Reset 4h 4h
0x27 - Clamp Position Register (PCLAMP) Bit 7-0 Function PCLAMP R/W R/W Description These bits set the clamping position from the PLL sync edge Reset 20h
0x28 - Vertical Control Register Bit 7-6 Function VLCKI R/W R/W Vertical lock in time. 0 = fastest 5-4 VLCKO R/W 3 = slowest. 0 Description Reset 0
Vertical lock out time. 0 = fastest 3 = slowest.
3
VMODE
R/W
This bit controls the vertical detection window. 1 = search mode. 0 = vertical count down mode.
0
2
DETV
R/W
1 = recommended for special application only. 0 = Normal Vsync logic
0
1
AFLD
R/W
Auto field generation control 0 = Off 1 = On
0
0
VINT
R/W
Vertical integration time control. 1 = long 0 = normal
0
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0x29 - Vertical Control II Bit 7-5 5-0 Function BSHT VSHT R/W R/W R/W Description Burst PLL center frequency control. Delayed Vsync position control in the increment of half line length or CC decoding line number for even field. Reset 0 15h
0x2A - Color Killer Level Control Bit 7-6 5-0 Function CKILMAX CKILMIN R/W R/W R/W Description These bits control the amount of color killer hysteresis. These bits control the color killer trip point. Reset 2 20h
0x2B - Comb Filter Control Bit 7-4 3-0 Function HTL VTL R/W R/W R/W Reserved Adaptive Comb filter combing strength control. Higher value provides stronger comb filtering. Description Reset 4 4
0x2C - Luma Delay and HSYNC Control Bit 7 Function CKLM R/W R/W Color Killer mode. 0 = normal 6-4 3-0 YDLY HSLEN R/W R/W 1 = fast 3h 7h Description Reset 0
Luma delay fine adjustment. This 2's complement number provide -4 to +3 unit delay control. It sets the pin output HSYNC pulse width in increment of 8 CLKX1 clock period. The minimum width is 8 CLKX1 period.
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0x2D - Miscellaneous Control Register I (MISC1) Bit 7 Function EVCNT R/W R/W Description 1 = Even field counter in special mode. 0 = Normal operation 6-4 HFLT R/W Pre-filter selection for scaler 1** = Bypass 000 = Auto selection based on Horizontal scaling ratio. 001 = Recommended for CIF size image 010 = Recommended for QCIF size image 011 = Recommended for ICON size image 3 TBC_EN R/W 1 = Internal TBC enabled.(test purpose only) 0 = TBC off. 2 BYPASS R/W 1 = Bypass output FIFO 0 = No bypass. 1 SYOUT R/W 1 = Hsync output is disabled when video loss is detected 0 = Hsync output is always enabled 0 HADV R/W This bit advances the HACTIVE and DVALID pin output by one data clock when set. 0 0 0 0 0 Reset 0
0x2E - Miscellaneous Control Register II (MISC2) Bit 7-6 Function HPM R/W R/W Description Horizontal PLL acquisition time. 3 = Fast 5-4 ACCT R/W 2 = Auto 1 = Mid 0 = Slow 2 Reset 2
ACC time constant 00 = No ACC 01 = slow 10 = medium 11 = fast
3-2
SPM
R/W
Burst PLL control. 0 = Slowest 1 = Slow 2 = Fast 3 = Fastest
1
1-0
CBW
R/W
Chroma low pass filter bandwidth control. Refer to filter curves.
1
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0x2F - Miscellaneous Control III (MISC3) Bit 7 Function NKILL R/W R/W Description 1 = Enable noisy signal color killer function in NTSC mode. 0 = Disabled. 6 PKILL R/W 1 = Enable automatic noisy color killer function in PAL mode. 0 = Disabled. 5 SKILL R/W 1 = Enable automatic noisy color killer function in SECAM mode. 0 = Disabled. 4 CBAL R/W 0 = Normal output 1 = special output mode. 3 FCS R/W 1 = Force decoder output value determined by CCS. 0 = Disabled. 2 LCS R/W 1 = Enable pre-determined output value indicated by CCS when video loss is detected. 0 = Disabled. 1 CCS R/W When FCS is set h or video loss condition is detected when igh LCS is set high, one of two colors display can be selected. 1 = Blue color. 0 = Black. 0 BST R/W 1 = Enable blue stretch. 0 = Disabled. 0 0 0 0 0 1 1 Reset 1
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0x30 - Macrovision Detection Bit 7 6 5 4 3 2 Function Reserved Reserved Reserved Reserved CSBAD MVCSN R/W R R R R R R 1 = Macrovision color stripe detection may be un-reliable 1 = Macrovision AGC pulse detected. 0 = Not detected. 1 CSTRIPE R 1 = Macrovision color stripe protection burst detected. 0 = Not detected. 0 CTYPE R This bit is valid only when color stripe protection is detected, i.e. Cstripe=1. 1 = Type 2 color stripe protection 0 = Type 3 color stripe protection 0 0 Description Reset 0 0 0 0 0 0
0x31 - Clamp Cntl2 Bit 7 6 Function CTEST YCLEN R/W R/W R/W Description Clamping control for debugging use. 1 = V channel clamp disabled 0 = Enabled. 5 CCLEN R/W 1 = V channel clamp disabled 0 = Enabled. 4 VCLEN R/W 1 = V channel clamp disabled 0 = Enabled. 3 GTEST R/W 1 = Test. 0 = Normal operation. 2 1 0 VLPF CKLY CKLC R/W R/W R/W Clamping filter control. Clamping current control 1. Clamping current control 2. 0 0 0 0 0 0 Reset 0 0
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0x32 - FILL DATA Bit 7-0 Function FILLDATA R/W R/W Description Fill data value for missing data byte in double word sliced VBI data output. Reset A0h
0x33 - VBI CNTL1 Bit 7-6 Function VBILPF R/W R/W Description VBI low pass filter selection. 00 = Disabled. 5-0 SDID R/W 01 = type1. 10 = type2. 11 = type3 22h Reset 0
Sliced VBI data identification code.
0x34 - VBI CNTL2 Bit 7 Function NODTEN R/W R/W Description 1 = Enabled embedded 'Vdloss' feature in 656 stream. 0 = Disabled. 6 SYRM R/W 1 = VBI output with sync removed. 0 = Raw VBI data output. 5 WSSEN R/W 1 = Enable WSS decoding. 0 = Disabled. 4-0 DID R/W ANC header framing code 11h 0 0 Reset 0
0x35 - MISC 4 Bit 7 Function ANCEN R/W R/W Description 1 = Enable ANC code output of sliced VBI data. 0 = Disabled. 6 TOUTHA R/W 1 = Sliced VBI (CC/EDS or WSS) data output during HACTIVE high period. 0 = Disabled. 5 VIPCFG R/W 1 = VIP task A control code. 0 = VIP task B control code. 1 0 Reset 0
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4-0
CCODDLI NE
R/W
These bits control the CC decoding line number in the case of Odd field.
15h
0x36 - Slice Level Bit 7-0 Function SLICE R/W R/W Description These bits define the VBI data initial slice level. Reset 72h
0x37 - WSS1 Bit 7 Function CRCERR R/W R Description This is the CRC error indicator for 525-line WSS. 1:CRC error.0:no error 6 5-0 WSSFLD WSS1 R R These bit indicates the detected WSS field information, 0=odd and 1=even. These bits represent the sliced WSS data bit 13 to 8. X X Reset 0
0x38 - WSS2 Bit 7-0 Function WSS2 R/W R Description These bits represent the sliced WSS bit 7 to 0. Reset X
0x39 - CSTATUS III Bit 5 4 3 2 1 0 Function WKAIR VSTD NINTL WSSDET EDSDET CCDET R/W R R R R R R 1 = Weak signal 1 = Standard signal 1 = Non-interlaced signal Description 0 = Nomal 0 = Non-standard signal 0 = interlaced signal Reset 0 0 0 0 0 0
1 = WSS data detected. 0 = Not detected. 1 = EDS data detected. 0 = Not detected. 1 = CC data detected. 0 = Not detected.
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0x3A - HFREF Bit 7-0 Function HFREF R/W R Description Horizontal line frequency indicator Reset X
0x3B - CLAMP MODE Bit 3-2 Function CLMD R/W R/W Clamping mode control. 0 = Sync top 1-0 PSP R/W 1 = Auto 2 = Pedestal 3 = N/A 1 2 = high Description Reset 1
Slice level control 0 = low 1 = Med
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Pin Diagram
1 VDD 2VD[15] 3VD[14] 4VD[13] 5VD[12] 6VD[11] 7VD[10] 8 VD[9] 9 VD[8] 10 VDD 11 GND 12 XTI 13 XTO 14 SIAD0 15 RST# 16 TEST1 17 TEST2 18SDAT 19SCLK 20 VDD 21 GND 22VD[7] 23VD[6] 24VD[5] 25VD[4] 26VD[3] 27VD[2] 28VD[1] 29VD[0] 30 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
GND CLKX2 OE# CLKX1 VDD GND VCLK GND VDD PDN GND CBFLAG VDD CCVALID VACTIVE MPOUT DVALID HACTIVE HSYNC GND
TW9903
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TMODE VSYNC FIELD GND VDD SIAD1 VCOM TS2DP AVDD AGND TS2DN C_PbIN1 TADCP C_PbIN0 AGND AVDD VREFP VQVD VREFN AGND AVDD EVC AGND MUX1 AGND MUX0 AGND MXOUT YIN AGND
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GND TDO TISVN TCK TRST# TMS TDI VDD GND SEL0 SEL1 AGND AGCOP AVDD MUX2 AGCON AGND AVDD CAGC MUX3
61
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TW9903 Pin Description
This section provides a detailed description of each pin for the TW9903. The pins are arranged in functional groups according to their associated interface. The active state of the signal is determined by the trailing symbol at the end of the signal name. A "#" symbol indicates that the signal is active or asserted at a low voltage level. When "#" is not present after the signal name, the signal is active at the high voltage level. The pin description also includes the buffer type used for that pin. I O OD I/O input pin output pin open drain output pin bi-directional input/output pin
Analog analog signal pin LVTTL low voltage TTL compatible signals with 3.3V outputs and 5V tolerant inputs. Analog Interface Pins
Pin# 45, 50, 55, 57 53 52 67 43, 46 I, analog O, analog I, analog I, analog O, analog I/O Pin Name MUX3, MUX2, MUX1, MUX0 MXOUT YIN C_PbIN0 AGCOP, AGCON Description These are the analog composite video inputs pins to the input selector. Four composite sources or three composites and one S-video source can be selected as the input. Unused pins should be connected to AGND. The output of the on-chip 4 -to-1 selector. It should be connected to the YIN pin. The input selected can be programmed through INFORM register. The analog composite or luma input to the Y-ADC. The analog chroma input to the C-ADC. The buffered AGC differential outputs that correspon to the AGCIN. It is for d test use only.
59 64
I, analog I/O, analog I/O, analog O, analog
EVC VREFP
Test pin. It should be left unconnected. The positive reference voltage for the ADC. It should be connected to AGND through 0.1uF capacitor. It can be optionally forced by external voltage reference source. The negative reference voltage for the ADC. It should be connected to AGND through a 0.1uF capacitor. It can be optionally forced by external voltage reference source. The common mode voltage output. It should be connected to analog GND through a 0.1uF capacitor. It can be optionally forced externally. 62
62
VREFN
74
VCOM
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Pin# 63 49 68 69 70 73
I/O I, analog I, Analog I, analog I, analog O, analog O, analog
Pin Name VQVD CAGC TADCP C_PbIN1 / TADCN TS2DN TS2DP
Description De-coupling pin. It should be connected with 0.1uF to AGND. Test pin. It should be left unconnected. Test pin. It should be connected to AGND during normal operation. The analog chroma input in the S-video mode or the analog Pr input in the component video input mode. It also doubles as a test pin. Test pin. It should be left unconnected during normal operation. Test pin. It should be left unconnected during normal operation.
Two Wire Interface Pins
Pin# 19 I/O I, LVTTL I/OD, LVTTL I, LVTTL I, LVTTL I, LVTTL Pin Name SCLK Description The MPU Serial interface Clock Line.
18
SDAT
The MPU Serial interface Data Line.
14 75 15
SIAD0 SIAD1 RST#
The MPU interface address select pin 0. This pin is used to select one of the four addresses that chip will respond. It is internally pulled down to ground. The MPU interface address select pin 1. This pin is used to select one of the four addresses that chip will respond. It is internally pulled down to ground. Master Reset Input. A logical zero for a minimum of four consecutive clock cycles is required to reset the device to its default state.
Video Timing Unit Pins
Pin# 82
I/O O, LVTTL
Pin Name HSYNC
Description Horizontal Sync Output. This signal indicates the beginning of a new line of video. This signal is typically 64 CLKx1 clock cycles wide, and can be programmed through HSLEN register. The falling edge of this output indicates the beginning of a new scan line of video. Note: The polarity of this pin is programmable through the POLARITY register.
79
O, LVTTL
VSYNC
Vertical Sync Output. This signal indicates the beginning of a new field of video. This signal is output coincident with the rising edge of CLKx2, and is normally six lines wide. The falling edge of VSYNC indicates the beginning of a new field of video. Note: The polarity of this pin is programmable through the POLARITY register.
83
O, LVTTL
HACTIVE
Active Video Output. This pin can be programmed to output the composite active or horizontal active signal via the Hactive register. It is a logicalhigh 63
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Pin#
I/O LVTTL
Pin Name
Description active or horizontal active signal via the Hactive register. It is a logicalhigh during the active/viewable periods of the video stream. The active region of the video stream is programmable. Note: The polarity of this pin is programmable through the POLARITY register.
94
O, LVTTL
VCLK
Video Clock Output. This pin provides a clo ck for video data strobing. The clock is available only during valid data period. This output is generated from CLKx1 (or CLKx2 in 8-bit mode), DVALID and, if programmed, HACTIVE. The phase of VCLK is inverted from the CLKx1 (or CLKx2) to ensure adequate s etup and hold time with respect to the data outputs. Output Enable Control. This pin controls the outputs of all video timing unit output pins and all clock interface output pins. All outputs are valid only when this pin is asserted low. This function is asynchronous. The threestated pins include: VD[15:0], HSYNC, VSYNC, HACTIVE, DVALID, CBFLAG, FIELD, VCLK, CLKx1, and CLKx2.
98
I, LVTTL
OE#
78
O, LVTTL
FIELD
Odd/Even Field Output. A high state on the FIELD pin indicates that an even field is being output. Note: The polarity of this pin is programmable through the POLARITY register.
89
O, LVTTL
CBFLAG
Cb Data Flag. A high state on this pin indicates that the current chroma byte contains Cb chroma information. Note: The polarity of this pin is programmab le through the POLARITY register.
2-9
O, LVTTL
VD[15:8]
22-29
I/O, LVTTL
VD[7:0]
Digitized Video Data Outputs. VD[0] is the least significant bit of the bus in 16-bit mode. VD[8] is the least significant bit of the bus in 8 -bit mode. The information is output with respect to CLKx1 rising edge in 16-bit mode, and CLKx2 rising edge in 8-bit mode. It can be programmed to output CCIR -656 compliant format. When data is output in 8-bit mode using VD[15:8], VD[7:0] can be used as general purpose I/O pins.
84
O, LVTTL
DVALID
Data Valid Output. This pin indicates when a valid pixel is being output onto the data bus. The format of this output pin can be programmed through the OPFORM register. Note: The polarity of this pin is programmable through the POLARITY register.
87
OD, LVTTL
CCVALID
A logical low on this pin indicates that the Closed Caption FIFO is half full (8 characters). This pin may be disabled. This open drain output requires a pullup resistor for proper operation. However, if closed captioning isnot implemented, this pin may be left unconnected. A logical high on this pin puts the device into power-down mode. This is equivalent to programming CLK_PDN high in the ADC register. Vertical Blanking Output. The falling edge of VACTIVE indicates the beginning of the active video lines in a field. This occurs VDELAY/2 lines after the rising edge of VSYNC. The rising edge of VACTIVE indicates the end of active video lines and occurs ACTIVE_LINES/2 lines after the falling edge of VACTIVE. VACTIVE is synchronized to the rising edge of CLKx1. Note: The polarity of the pin is programmable through the POLARITY register.
91 86
I, LVTTL O, LVTTL
PDN VACTIVE
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Pin# 85
I/O O, LVTTL
Pin Name MPOUT
Description Multi-purpose output pin. The output function can be selected by RTSEL of register 0x19. Note: When LVALID is selected, the polarity of this pin is programmable through the POLARITY register.
80
I, LVTTL
TMODE
This pin is used to enable the in-circuit test mode. It should be connected to GND through a 10K ohm pull-down resistor for in-circuit test or tied to GND directly for others. When this pin is asserted (active high), pin TEST1 and TEST2 will determine the test to be performed. Test pin 1. See Test mode section for description. Test pin 2. See Test mode section for description.
16 17
I, LVTTL I, LVTTL
TEST1 TEST2
Clock Interface Pins
Pin# 12 I I/O Pin Name XTI Description Clock Zero pins. A 27MHz fundamental (or third harmonic) crystal can be connected directly to these pins, or a single -ended oscillator can be connected to XTI. For Crystal 27MHz connection 1x clock output. The frequency of this clock is half of the crystal frequency, i.e. 13.5Mhz when 27Mhz crystal is used. 2x clock output. The frequency of this clock is the same as the crystal frequency, i.e. 27Mhz when 27Mhz crystal is used.
13 97 99
O O, LVTTL O, LVTTL
XTO CLKx1 CLKx2
Test Pins
Pin# 34 36 37 32 33 35 41 40 I/O I/O, LVTTL I/O, LVTTL I/O, LVTTL I/O, LVTTL I/O, LVTTL I/O, LVTTL I, LVTTL I, LVTTL Pin Name TCK TMS TDI TDO TISVN TRST SEL1 SEL0 Description Test pin. It should be connected to GND during normal operation. Test pin. It should be connected to GND during normal operation. Test pin. It should be connected to GND during normal operation. Test pin. It should be connected to GND during normal operation. Test pin. It should be connected to GND duringnormal operation. Test pin. It should be connected to GND during normal operation. Y input MUX control 1. Y input MUX control pin 0. 65
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Power and Ground Pins
Pin# 1, 10, 20, 30, 38, 76, 88, 92, 96 44, 48, 60, 65, 72 11, 21, 31, 39, 77, 81, 90, 93, 95, 100 42, 47, 54, 56, 58, 61, 66, 71, 51 P
I/O
Pin Name VDD
Description +3.3 V Power supply for digital circuitry. All VDD pins must be connected together as close to the device as possible. A 0.1 F ceramic capacitor should be connected between each group of VDD pins and the ground plane as close to the device as possible. Power supply for analog circuitry. All AVDD pins must be connected together as close to the device as possible. A 0.1 F ceramic capacitor should be connected between each group of AVDD pins and the ground plane as close to the device as possible. Ground for digital circuitry. All GND pins must be connected together as close to the device as possible.
P
AVDD +3.3V
G
GND
G
AGND
Ground for analog circuitry. All AGND pins must be connected together as close to the device as possible.
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Parametric Information
AC/DC Electrical Parameters
Table 7. Absolute Maximum Ratings Parameter AVDD (measured to AGND) V DD (measured to DGND) Voltage on any signal pin (See the note below) Analog Input Voltage Storage Temperature Junction Temperature Vapor Phase Soldering(15 Seconds) Symbol VDDAM VDDM TS TJ T VSOL Min DGND - 0.5 AGND - 0.5 -65 Typ Max 4.8 4.8 VDDAM + 0.5 VDDM + 0.5 +150 +125 +220 Units V V V V C C C
NOTE: Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional
operation at these or any other conditions above those listed in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device employs high-impedance CMOS devices on all signal pins. It must be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V or drops below ground by more than 0.5 V can induce destructive latchup. Table 8. characteristics Parameter Supply Power Supply -- Analog Power Supply -- Digital Maximum |V DD - AVDD| MUX0, MUX1 and MUX2 Input Range (AC coupling required) PRIN Amplitude Range (AC coupling required) Ambient Operating Temperature Analog Supply current Digital Supply current Digital Inputs Input High Voltage (TTL) Input Low Voltage (TTL) Input High Voltage (XTI) Input Low Voltage (XTI) Input High Current (V IN =V DD ) Input Low Current (V IN =GND) Input Capacitance (f=1 MHz, V
IN
Symbol
Min
Typ
Max
Units
VDDA VDD
3.15 3.15 0.5 0.5 0 -
3.3 3.3 1.00 1.00 30 90
3.45 3.45 0.3 2.00 2.00 +70 -
V V V V V C mA mA
TA Iaa Idd
V IH V IL V IH V IL I IH I IL =2.4 V) C
IN
2.0 2.0 GND -0.5 -
5
V DDM + 0.5 0.8 V DDM + 0.5 1.0 10 -10 -
V V V V
A A
pF
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TW9903
Parameter Digital Outputs Output High Voltage (I OH = -4 mA) Output Low Voltage (I OL = 4 mA) 3-State Current Output Capacitance Analog Input Analog Pin Input voltage Analog Pin Input Capacitance ADCs ADC resolution ADC integral Non -linearity ADC differential non-linearity ADC clock rate Video bandwidth (-3db) Horizontal PLL Line frequency (50Hz) Line frequency (60Hz) static deviation Subcarrier PLL subcarrier frequency (NTSC-M) subcarrier frequency (PAL-BDGHI) subcarrier frequency (PAL-M) subcarrier frequency (PAL-N) lock in range Crystal spec nominal frequency (fundamental) deviation Temperature range load capacitance series resistor Oscillator Input nominal frequency deviation duty cycle
Symbol
Min
Typ
Max
Units
V OH V OL I OZ CO
2.4 -
0.2 5
V DD 0.4 10 -
V V
A
pF
Vi CA
-
1 7
-
Vpp pF
ADCR AINL ADNL fADC BW
24 -
10
1 1
27 10
30 -
bits LSB LSB MHz MHz
fLN fLN D fH
-
15.625 15.734 -
6.2
KHz KHz %
fSC fSC fSC fSC D fH
400
3579545 4433619 3575612 3582056 -
-
Hz Hz Hz Hz Hz
Ta CL RS
0 -
27 20 80
50
70 -
MHz ppm o C pF Ohm
-
27 -
50 55
MHz ppm %
Parameter
Symbol 68
Min
Typ
Max
Units
TECHWELL, INC.
REV. 0.92 ( B ) 06/02/2002
TW9903
Output CLK CLKx1 CLKx2 CLKx1 Duty Cycle CLKx2 Duty Cycle CLKx2 to CLKx1 Delay CLKx1 to Data Delay CLKx2 to Data Delay CLKx1 (Falling Edge) to VCLK (Rising Edge) CLKx2 (Falling Edge) to VCLK (Rising Edge) Output Video Data 8-bit Mode (1) Data to VCLK (Rising Edge) Delay VCLK (Rising Edge) to Data Delay 16-bit Mode (1) Data to VCLK (Rising Edge) Delay VCLK (Rising Edge) to Data Delay OE# Asserted to Data Bus Driven OE# Asserted to Data Valid OE# Negated to Data Bus Not Driven
4 5 6 41 42
12 24 -
13.5 27 5 5 0 0
15 30 55 55 2 -
MHz MHz % % ns ns ns ns ns
7b 8b 7a 8a
0 -
18 18 37 37 -
100 100
ns ns ns ns ns ns ns
Clock Timing Diagram
1 XT 3 2
(8-bit output mode)
VCLK Data 6 CLKx2 4 7b 8b 42
(16-bit output mode)
41 CLKx1
VCLK Data
5
7a
8a
TECHWELL, INC.
69
REV. 0.92 ( B ) 06/02/2002
TW9903
Application Information
Video Input Interface The TW9903 has a built-in 4:1 input MUX for software controllable input selections. This MUX can be used to select three composite video sources and one S-Video source or two composite video sources, one S-video and one component video source. The output of the MUX (MUXOUT) should be connected to YIN directly or through a 0.1uF capacitor. The chroma of the S-Video input should be connected to C_PBIN0 or C_PBIN1 of the C-Channel A/D converter. For a typical application, a video input should be first terminated with a 75 ohm resistor before it is AC coupled by a 0.1uF capacitor to the input of the MUX. A/D Converter The TW9903 has three internal A/D converters to cover all possible analog video signal sources. The reference supply generator for the A/D converter is also on-chip. For a better noise immunity, VREFP, VREFN, VCOM and VQVD should be connected through a 0.1uF capacitor to AGND. Clamping/AGC The TW9903 has built-in automatic clamping control circuitry. No extra external component is needed for this operation. The clamping loop gain can be controlled through register setting. The TW9903 also has built-in automatic AGC control circuitry. The AGC loop gain can also be controlled by register. The AGC loop response time is also register programmable. Clock Generation The TW9903 requires one 27MHz crystal connected to XTI and XTO for all format decoding. The default crystal type should be 27MHz, fundamental mode, 20pF load capacitance or less, + 50ppm, and with series resistance of 80 ohm or less. An external clock source of 27MHz can also be connected to the XTI input in place of the crystal. For True Square Pixel mode applications, a 24.54MHz crystal for 60Hz field rate source and a 29.5MHz crystal for 50Hz field rate source should be used. In this case, the bit FC27 of registers 0x02 should be set to '0' for proper operation. A typical 27MHz third overtone crystal circuit is shown in the following figure. In the case of using 27MHz fundamental mode crystal, the C1 and L1 can be omitted. Power-Up After power-up, the TW9903 registers have unknown values. The RST# pin must be asserted and released to bring all registers to its default values. After reset, the TW9903 data outputs are tristated. The OPFORM register should be written after reset to enable outputs desired.
TECHWELL, INC.
70
REV. 0.92 ( B ) 06/02/2002
TW9903 Application Schematics
15p 4.7k 270 10uH 47p 100p 1.5k
3.3/5V
CVBS1
75
filter 0.1u
MUX0
SCL
1.5k
75
filter 0.1u 3.3u 330p 330p 75 0.1u
MUX1
SDA
S-Video
CIN0
VD0-15
Video Timing
TW9903
SIAD1 SIAD0 TMODE TEST1 TEST2 OEB PDN
VREFP
0.1uF
VREFN
0.1uF
MUXOUT YIN
VCOM
0.1uF
VQVD
0.1uF
3.3V RST#
C1, 33pf L1, 10uH
DVDD
0.1uF
DGND AVDD XTI
0.1uF
GND Filtered 3.3V
See Text
22pf
1Mohm 22pf
27M
AGND XTO
Isolated GND plane
AGND Note: All unused digital input pins should be tied to DGND DGND Typical TW9903 External Circuitry
TECHWELL, INC.
71
REV. 0.92 ( B ) 06/02/2002
TW9903
PCB Layout Considerations The PCB layout should be done to minimize the power and ground noise on the TW9903. This is done by good power de-coupling with minimum lead length on the de-coupling capacitors; wellfiltered and regulated analog power input shielding and ground plane isolation. The ground plane should cover most of the PCB area with separated digital and analog ground planes surrounding the chip. These two planes should be at the same electrical potential and connected together near the power supply. The following figure shows a ground plane layout example.
DGND TW9903
Card Edge AGND
Power Supply Return
To minimize crosstalk, the digital signals of TW9903 should be separated from the analog circuitry. Moreover, the digital signals should not cross over the analog power and ground plane. Parallel running of digital lines for long distance should also be avoided.
TECHWELL, INC.
72
REV. 0.92 ( B ) 06/02/2002
TW9903 100-pin PQFP Package Mechanical Drawing
A A1 A2 E E1 E2
e D D2
TW9903
D1
b
Top View
L L1 c
Symbol A A1 A2 b c e D D1 D2 E E1 E2 L L1
Min. --0.25 2.55 0.22 0.11 22.95
0.73
Millimeter Nom. ----2.72 0.30 0.15 0.65 Basic 23.2 20.00 Basic 18.85 Ref 17.20 Basic 14.00 basic 12.35 Ref --1.60 Ref
Max. 3.40 --3.05 0.38 0.23 23.45
1.03
Inch Nom. ----0.107 0.012 0.006 0.026 Basic 0.903 0.913 0.787 Basic 0.742 Ref 0.677 Basic 0.551 Basic 0.486 0.029 --0.063Ref Min. --0.010 0.100 0.009 0.004
Max. 0.134 --0.120 0.015 0.009 0.923
0.041
Note: 1. Dimension of D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimension D1 and E1 do include mold mismatch and are determined at datum plane.
2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed. The maximum b dimension by more than 0.08mm dambar cannot be located on the lower radius or the lead root.
TECHWELL, INC.
73
REV. 0.92 ( B ) 06/02/2002
TW9903 100-pin LQFP Package Mechanical Drawing
A E A1 1 A2 E1 E2
b
TW9903
e D D1 D2 Top View
L L1 c Symbol
A A1 A2 b c e D D1 D2 E E1 E2 L L1
Min. --0.05 1.35 0.13 0.09
0.45
Millimeter Nom. ----1.40 0.16 0.10 0.4 Basic 14.0 Basic 12.00 Basic 9.60 14.0 Basic 12.00 Basic 9.60 0.60 1.00 Ref
Max. 1.60 0.15 1.45 0.23 0.20
0.75
Inch Min. Nom. Max. ----0.063 0.002 --0.006 0.053 0.055 0.057 0.005 0.006 0.009 0.004 --0.008 0.016 Basic 0.551 Basic 0.472 Basic 0.378 0.551Basic 0.472 Basic 0.378 0.018 0.024 0.030 0.039Ref
Note: 1. Dimension of D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimension D1 and E1 do include mold mismatch and are determined at datum plane. 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed. The maximum b dimension by more than 0.08mm dambar cannot be located on the lower radius or the lead root.
TECHWELL, INC.
74
REV. 0.92 ( B ) 06/02/2002

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